公开(公告)号：US10283588B2

公开(公告)日：2019-05-07

申请号：US15845930

申请日：2017-12-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Emmanuel Perrin

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L21/8238

Abstract: An integrated circuit may include an SOI substrate having a buried insulating layer, and a semiconductor film above the buried insulating layer. The semiconductor film may have first patterns in a first zone defining gate regions of first MOS transistors and also first dummy gate regions. The first zone may include two domains having a space therebetween, and the space may be filled by at least one insulating material and be situated between two dummy gate regions above a region of the supporting substrate without any insulating trench.

公开(公告)号：US20180108731A1

公开(公告)日：2018-04-19

申请号：US15845930

申请日：2017-12-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Emmanuel Perrin

IPC: H01L29/06 ,  H01L21/84 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/76283 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628

Abstract: An integrated circuit may include an SOI substrate having a buried insulating layer, and a semiconductor film above the buried insulating layer. The semiconductor film may have first patterns in a first zone defining gate regions of first MOS transistors and also first dummy gate regions. The first zone may include two domains having a space therebetween, and the space may be filled by at least one insulating material and be situated between two dummy gate regions above a region of the supporting substrate without any insulating trench.

公开(公告)号：US09876076B2

公开(公告)日：2018-01-23

申请号：US14956594

申请日：2015-12-02

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Emmanuel Perrin

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/76283 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628

Abstract: An integrated circuit may include an SOI substrate having a buried insulating layer, and a semiconductor film above the buried insulating layer. The semiconductor film may have first patterns in a first zone defining gate regions of first MOS transistors and also first dummy gate regions. The first zone may include two domains having a space therebetween, and the space may be filled by at least one insulating material and be situated between two dummy gate regions above a region of the supporting substrate without any insulating trench.

公开(公告)号：US20130099322A1

公开(公告)日：2013-04-25

申请号：US13659768

申请日：2012-10-24

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Emmanuel Perrin ,  Gregory Bidal ,  Raul Andres Bianchi

IPC: H01L29/78 ,  H01L21/283

CPC classification number: H01L21/76237 ,  H01L21/28229 ,  H01L21/823481 ,  H01L29/513 ,  H01L29/518

Abstract: A method for defining an insulating area in a semiconductor substrate, including a step of forming of a bonding layer on the walls and the bottom of a trench defined in the substrate. A step of passivation of the apparent surface of said bonding layer, at least close to the surface of said semiconductor substrate.

Abstract translation: 一种用于限定半导体衬底中的绝缘区域的方法，包括在衬底中限定的沟槽的壁和底部上形成接合层的步骤。 至少靠近所述半导体衬底的表面钝化所述接合层的表观表面的步骤。