Invention Grant
- Patent Title: Forming method of superposition checking mark, manufacturing method of a semiconductor device and semiconductor device
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Application No.: US15057406Application Date: 2016-03-01
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Publication No.: US09881874B2Publication Date: 2018-01-30
- Inventor: Kenichi Yasuda , Shinya Arai
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Minato-ku
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L23/544 ; H01L21/033 ; H01L21/768 ; H01L27/11582 ; H01L21/28 ; H01L21/66 ; H01L21/027
Abstract:
According to one embodiment, a forming method of superposition checking marks includes forming a first superposition checking mark to have a first step with respect to an arrangement surface for the first superposition checking mark, forming an opaque film having a second step resulting from the first step on the arrangement surface, and forming on the opaque film a second superposition checking mark provided with a transparent film allowing observation of the second step.
Public/Granted literature
Information query
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