Invention Grant
- Patent Title: Scalable event handling in multi-threaded processor cores
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Application No.: US14581285Application Date: 2014-12-23
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Publication No.: US09886396B2Publication Date: 2018-02-06
- Inventor: Roger Gramunt , Rammohan Padmanabhan , Ramon Matas , Neal S. Moyer , Benjamin C. Chaffin , Avinash Sodani , Alexey P. Suprun , Vikram S. Sundaram , Chung-Lun Chan , Gerardo A. Fernandez , Julio Gago , Michael S. Yang , Aditya Kesiraju
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott LLP
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/44 ; G06F12/12 ; G06F12/122 ; G06F9/48 ; G06F9/38

Abstract:
In one embodiment, a processor includes a frontend unit having an instruction decoder to receive and to decode instructions of a plurality of threads, an execution unit coupled to the instruction decoder to receive and execute the decoded instructions, and an instruction retirement unit having a retirement logic to receive the instructions from the execution unit and to retire the instructions associated with one or more of the threads that have an instruction or an event pending to be retired. The instruction retirement unit includes a thread arbitration logic to select one of the threads at a time and to dispatch the selected thread to the retirement logic for retirement processing.
Public/Granted literature
- US20160179533A1 SCALABLE EVENT HANDLING IN MULTI-THREADED PROCESSOR CORES Public/Granted day:2016-06-23
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