公开(公告)号：US09886396B2

公开(公告)日：2018-02-06

申请号：US14581285

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Roger Gramunt ,  Rammohan Padmanabhan ,  Ramon Matas ,  Neal S. Moyer ,  Benjamin C. Chaffin ,  Avinash Sodani ,  Alexey P. Suprun ,  Vikram S. Sundaram ,  Chung-Lun Chan ,  Gerardo A. Fernandez ,  Julio Gago ,  Michael S. Yang ,  Aditya Kesiraju

IPC: G06F9/30 ,  G06F9/44 ,  G06F12/12 ,  G06F12/122 ,  G06F9/48 ,  G06F9/38

CPC classification number: G06F12/122 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/4806 ,  G06F2212/62

Abstract: In one embodiment, a processor includes a frontend unit having an instruction decoder to receive and to decode instructions of a plurality of threads, an execution unit coupled to the instruction decoder to receive and execute the decoded instructions, and an instruction retirement unit having a retirement logic to receive the instructions from the execution unit and to retire the instructions associated with one or more of the threads that have an instruction or an event pending to be retired. The instruction retirement unit includes a thread arbitration logic to select one of the threads at a time and to dispatch the selected thread to the retirement logic for retirement processing.