- Patent Title: Techniques for forming interconnects in porous dielectric materials
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Application No.: US15225392Application Date: 2016-08-01
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Publication No.: US09887161B2Publication Date: 2018-02-06
- Inventor: Christopher J. Jezewski , David J. Michalak , Kanwal Jit Singh , Alan M. Myers
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Finch & Maloney PLLC
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/532 ; H01L21/768 ; H01L21/3105 ; H01L21/311 ; H01L23/528 ; H01L21/02

Abstract:
Techniques are disclosed for forming interconnects in porous dielectric materials. In accordance with some embodiments, the porosity of a host dielectric layer may be reduced temporarily by stuffing its pores with a sacrificial pore-stuffing material, such as titanium nitride (TiN), titanium dioxide (TiO2), or other suitable sacrificial material having a high etch selectivity compared to the metallization and dielectric material of the interconnect. After interconnect formation within the stuffed dielectric layer, the sacrificial pore-stuffing material can be removed from the pores of the host dielectric. In some cases, removal and curing can be performed with minimal or otherwise negligible effect on the dielectric constant (κ-value), leakage performance, and/or time-dependent dielectric breakdown (TDDB) properties of the host dielectric layer. Some embodiments can be utilized, for example, in processes involving atomic layer deposition (ALD)-based and/or chemical vapor deposition (CVD)-based backend metallization of highly porous, ultra-low-κ (ULK) dielectric materials.
Public/Granted literature
- US20160343665A1 TECHNIQUES FOR FORMING INTERCONNECTS IN POROUS DIELECTRIC MATERIALS Public/Granted day:2016-11-24
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