Invention Grant
- Patent Title: Transaction response modification within interconnect circuitry
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Application No.: US14874801Application Date: 2015-10-05
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Publication No.: US09892072B2Publication Date: 2018-02-13
- Inventor: Andrew David Tune , Arthur Brian Laughton , Daniel Adam Sara , Sean James Salisbury , Peter Andrew Riocreux
- Applicant: ARM LIMITED
- Applicant Address: GB Cambridge
- Assignee: ARM Limited
- Current Assignee: ARM Limited
- Current Assignee Address: GB Cambridge
- Agency: Nixon & Vanderhye P.C.
- Priority: GB1418142.4 20141014
- Main IPC: G06F13/00
- IPC: G06F13/00 ; G06F13/364 ; G06F13/42

Abstract:
Interconnect circuitry for connecting transaction masters to transaction slaves includes response modification circuitry. The response modification circuitry includes shortlist buffer circuitry storing identification for modification target transaction responses. The response modification circuitry uses this identification data to identify among a stream of transaction responses in transit a modification target transaction response. The response modification circuitry then serves to form a modified transaction response to be sent in place of the modification target transaction response to the transaction master.
Public/Granted literature
- US20160103776A1 TRANSACTION RESPONSE MODIFICATION WITHIN INTERCONNECT CIRCUITRY Public/Granted day:2016-04-14
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