公开(公告)号：US09928195B2

公开(公告)日：2018-03-27

申请号：US14959170

申请日：2015-12-04

申请人： ARM LIMITED

发明人： Andrew David Tune ,  Peter Andrew Riocreux ,  Sean James Salisbury ,  Daniel Adam Sara ,  George Robert Scott Lloyd

IPC分类号： G06F13/00 ,  G06F13/36 ,  G06F13/38 ,  G06F13/42 ,  G06F13/364 ,  G06F12/0815 ,  G06F13/40

CPC分类号： G06F13/364 ,  G06F12/0815 ,  G06F13/404 ,  G06F13/4282 ,  G06F2212/621

摘要： An interconnect, and method of operation of an interconnect, are provided for connecting a plurality of master devices and a plurality of slave devices. Hazard management circuitry is used to serialize transactions to overlapping addresses. In addition, gating circuitry ensures ordered write observation (OWO) behavior at an interface to one or more of the master devices, the gating circuitry receiving write address transfers of write transactions and performing a gating operation to gate onward propagation of the write address transfers to the slave devices in order to ensure the OWO behavior. The gating circuitry performs the gating operation under control of the hazard management circuitry. Hence, for write transactions that are subjected to hazard checking by the hazard management circuitry, this removes the need to implement any other processes to specifically manage OWO behavior for those write transactions.

公开(公告)号：US10289587B2

公开(公告)日：2019-05-14

申请号：US15139559

申请日：2016-04-27

申请人： ARM Limited

发明人： Ian David Andrews ,  Andrew David Tune ,  Daniel Adam Sara ,  George Robert Scott Lloyd

IPC分类号： G06F13/40 ,  G06F13/16 ,  G06F13/42 ,  G06F13/36

摘要： A crossbar switch comprises two or more data inputs 10, two or more data outputs 100, a buffer 30 between the inputs and the outputs, an arbiter 52 associated with each output and configured to select data from one of the inputs when there is contention at the output, a bypass 32 associated with the buffer so that the buffer can be enabled or disabled, and a buffer controller 60 configured to enable or disable the buffer. The buffer controller further includes an accumulator 70 configured to assess whether a time-based average of the contention rate, or an average injection rate, at the output associated with the buffer, has reached a predetermined threshold. This prevents the buffer being enabled when the contention is only intermittent, which reduces power consumption without significant loss of performance.

公开(公告)号：US11314675B2

公开(公告)日：2022-04-26

申请号：US16659762

申请日：2019-10-22

申请人： Arm Limited

发明人： Guanghui Geng ,  Andrew David Tune ,  Daniel Adam Sara ,  Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal

IPC分类号： G06F13/42 ,  G06F13/364 ,  G06F13/40 ,  G06F12/0888 ,  G06F12/0815

摘要： A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.

公开(公告)号：US09892072B2

公开(公告)日：2018-02-13

申请号：US14874801

申请日：2015-10-05

申请人： ARM LIMITED

发明人： Andrew David Tune ,  Arthur Brian Laughton ,  Daniel Adam Sara ,  Sean James Salisbury ,  Peter Andrew Riocreux

IPC分类号： G06F13/00 ,  G06F13/364 ,  G06F13/42

CPC分类号： G06F13/364 ,  G06F13/4282

摘要： Interconnect circuitry for connecting transaction masters to transaction slaves includes response modification circuitry. The response modification circuitry includes shortlist buffer circuitry storing identification for modification target transaction responses. The response modification circuitry uses this identification data to identify among a stream of transaction responses in transit a modification target transaction response. The response modification circuitry then serves to form a modified transaction response to be sent in place of the modification target transaction response to the transaction master.