Invention Grant
- Patent Title: Double-sided semiconductor package and dual-mold method of making same
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Application No.: US15089151Application Date: 2016-04-01
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Publication No.: US09893017B2Publication Date: 2018-02-13
- Inventor: Il Kwon Shim , Pandi C. Marimuthu , Yaojian Lin
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Brian M. Kaufman; Robert D. Atkins
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L21/48 ; H01L25/10 ; H01L21/56 ; H01L21/683 ; H01L23/31 ; H01L23/00 ; H01L25/16

Abstract:
A semiconductor device comprises a first conductive layer formed on a carrier over an insulating layer. A portion of the insulating layer is removed prior to forming the first conductive layer. A first semiconductor die is disposed over the first conductive layer. A discrete electrical component is disposed over the first conductive layer adjacent to the first semiconductor die. A first encapsulant is deposited over the first conductive layer and first semiconductor layer. A conductive pillar is formed through the first encapsulant between the first conductive layer and second conductive layer. A second encapsulant is deposited around the first encapsulant, first conductive layer, and first semiconductor die. A second conductive layer is formed over the first semiconductor die, first encapsulant, and second encapsulant opposite the first conductive layer. The carrier is removed after forming the second conductive layer. A semiconductor package is mounted to the first conductive layer.
Public/Granted literature
- US20160300797A1 Double-Sided Semiconductor Package and Dual-Mold Method of Making Same Public/Granted day:2016-10-13
Information query
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