Invention Grant
- Patent Title: Method of forming internal dielectric spacers for horizontal nanosheet FET architectures
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Application No.: US15276784Application Date: 2016-09-26
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Publication No.: US09905672B2Publication Date: 2018-02-27
- Inventor: Wei-E Wang , Mark S. Rodder , Borna J. Obradovic , Dharmendar Reddy Palle , Joon Goo Hong
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR
- Agency: Renaissance IP Law Group LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L29/66 ; H01L21/02 ; H01L29/08 ; H01L29/10 ; H01L29/04

Abstract:
A method to form a nanosheet stack for a semiconductor device includes forming a stack of a plurality of sacrificial layers and at least one channel layer on an underlayer in which a sacrificial layer is in contact with the underlayer, each channel layer being in contact with at least one sacrificial layer, the sacrificial layers are formed from SiGe and the at least one channel layer is formed from Si; forming at least one source/drain trench region in the stack to expose surfaces of the SiGe sacrificial layers and a surface of the at least one Si channel layer; and oxidizing the exposed surfaces of the SiGe sacrificial layers and the exposed surface of the at least one Si layer in an environment of wet oxygen, or ozone and UV.
Public/Granted literature
- US20170338328A1 METHOD OF FORMING INTERNAL DIELECTRIC SPACERS FOR HORIZONTAL NANOSHEET FET ARCHITECTURES Public/Granted day:2017-11-23
Information query
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