Invention Grant
- Patent Title: Methods and apparatus to optimize instructions for execution by a processor
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Application No.: US14737058Application Date: 2015-06-11
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Publication No.: US09916164B2Publication Date: 2018-03-13
- Inventor: Vineeth Mekkat , Girish Venkatasubramanian , Howard H. Chen
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Hanley, Flight & Zimmerman, LLC
- Main IPC: G06F9/38
- IPC: G06F9/38 ; G06F9/30 ; G06F9/45

Abstract:
Methods, apparatus, systems and articles of manufacture are disclosed herein. An example apparatus includes an instruction profiler to identify a predicated block within instructions to be executed by a hardware processor. The example apparatus includes a performance monitor to access a mis-prediction statistic based on an instruction address associated with the predicated block. The example apparatus includes a region former to, in response to determining that the mis-prediction statistic is above a mis-prediction threshold, include the predicated block in a predicated region for optimization.
Public/Granted literature
- US20160364240A1 METHODS AND APPARATUS TO OPTIMIZE INSTRUCTIONS FOR EXECUTION BY A PROCESSOR Public/Granted day:2016-12-15
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