Method, apparatus, and system for improving semiconductor device writeability at row/bit level through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS, wherein the first array supply voltage and the second array supply voltage are greater than the operational array supply voltage. By virtue of BTI, application of the first array supply voltage may lead to improved writeability of one or more cells of the device.