公开(公告)号：US09601187B1

公开(公告)日：2017-03-21

申请号：US15046983

申请日：2016-02-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Akhilesh Gautam ,  Randy W. Mann ,  William McMahon ,  Yoann Mamy Randriamihaja ,  Yuncheng Song

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/06

CPC classification number: G11C29/56 ,  G11C7/04 ,  G11C8/08 ,  G11C11/418

Abstract: We disclose methods, apparatus, and systems for improving semiconductor device yield and/or reliability through bias temperature instability (BTI). One device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line controls access to each pass gate of a first number of cells; a word line driver electrically connected to each word line; and a control line configured to provide an operational write voltage or a first write voltage to each word line through the word line driver. By virtue of BTI, application of the first write voltage may lead to improved stability of data desired to be read from one or more cells of the device.

公开(公告)号：US10068660B2

公开(公告)日：2018-09-04

申请号：US15615660

申请日：2017-06-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Akhilesh Gautam ,  Randy W. Mann ,  William McMahon ,  Yoann Mamy Randriamihaja ,  Yuncheng Song

IPC: G11C29/00 ,  G11C29/52 ,  G11C11/419 ,  G11C11/412

Abstract: We disclose methods, apparatus, and systems for improving semiconductor device writeability through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS through the array VCS driver.

公开(公告)号：US09916212B2

公开(公告)日：2018-03-13

申请号：US15047395

申请日：2016-02-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Akhilesh Gautam ,  Randy W. Mann ,  William McMahon ,  Yoann Mamy Randriamihaja ,  Yuncheng Song

IPC: G06F11/00 ,  G06F11/16 ,  G06F11/20

CPC classification number: G06F11/167 ,  G06F11/2015 ,  G06F2201/85 ,  G11C7/04 ,  G11C11/419 ,  G11C29/00 ,  G11C29/028 ,  G11C29/52

Abstract: Method, apparatus, and system for improving semiconductor device writeability at row/bit level through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS, wherein the first array supply voltage and the second array supply voltage are greater than the operational array supply voltage. By virtue of BTI, application of the first array supply voltage may lead to improved writeability of one or more cells of the device.

公开(公告)号：US09601188B1

公开(公告)日：2017-03-21

申请号：US15047139

申请日：2016-02-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Akhilesh Gautam ,  Randy W. Mann ,  William McMahon ,  Yoann Mamy Randriamihaja ,  Yuncheng Song

IPC: G11C11/00 ,  G11C11/419

CPC classification number: G11C29/70 ,  G11C7/04 ,  G11C8/08 ,  G11C11/418 ,  G11C29/56

Abstract: We disclose methods, apparatus, and systems for improving semiconductor device yield and/or reliability through bias temperature instability (BTI). One device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line controls access to each pass gate of a first number of cells; a word line driver electrically connected to each word line; a row decoder configured to authorize or deauthorize a write voltage to each word line through the word line driver, wherein the write voltage is selected from an operational write voltage or a first write voltage; and a control line configured to provide an operational write voltage or a first write voltage to each word line authorized by the row decoder, wherein the first write voltage is greater than an operational write voltage.

公开(公告)号：US20170271032A1

公开(公告)日：2017-09-21

申请号：US15615660

申请日：2017-06-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Akhilesh Gautam ,  Randy W. Mann ,  William McMahon ,  Yoann Mamy Randriamihaja ,  Yuncheng Song

IPC: G11C29/52 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C29/52 ,  G11C7/04 ,  G11C11/412 ,  G11C11/419

Abstract: We disclose methods, apparatus, and systems for improving semiconductor device writeability through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS through the array VCS driver.

公开(公告)号：US09548136B2

公开(公告)日：2017-01-17

申请号：US14664959

申请日：2015-03-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vivek Joshi ,  Sriram Balasubramanian ,  Chad Weintraub ,  Yoann Mamy Randriamihaja ,  William McMahon

IPC: G11C29/00 ,  G11C29/04 ,  G11C11/419

CPC classification number: G11C29/04 ,  G11C11/412 ,  G11C11/419 ,  G11C29/56008

Abstract: A method and an apparatus for identifying non-intrinsic defect bits from a population of failing bits for failure analysis to characterize the extrinsic failure mechanisms is provided. Embodiments include performing a failure mode test on a bank of a memory array at different low VDD; determining optimal bank size to observe plateaus of fail counts; determining fail counts of the bank at each different low VDD; determining a plateau of the fail counts; determining whether the plateau represents extrinsic bits of the bank; and submitting the extrinsic bits for root cause analysis.

Abstract translation: 提供了一种用于从用于故障分析的故障位群体中识别非本征缺陷位以表征外在故障机制的方法和装置。 实施例包括在不同的低VDD下对存储器阵列进行故障模式测试; 确定最佳银行规模以观察失败计数的平稳度; 在每个不同的低VDD处确定存储体的故障计数; 确定失败计数的高原; 确定平台是否代表银行的外在位; 并提交根本原因分析的外在位。

公开(公告)号：US20170242759A1

公开(公告)日：2017-08-24

申请号：US15047395

申请日：2016-02-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Akhilesh Gautam ,  Randy W. Mann ,  William McMahon ,  Yoann Mamy Randriamihaja ,  Yuncheng Song

IPC: G06F11/16 ,  G06F11/20

CPC classification number: G06F11/167 ,  G06F11/2015 ,  G06F2201/85 ,  G11C7/04 ,  G11C11/419 ,  G11C29/00 ,  G11C29/028 ,  G11C29/52

Abstract: Method, apparatus, and system for improving semiconductor device writeability at row/bit level through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS, wherein the first array supply voltage and the second array supply voltage are greater than the operational array supply voltage. By virtue of BTI, application of the first array supply voltage may lead to improved writeability of one or more cells of the device.

公开(公告)号：US09704600B1

公开(公告)日：2017-07-11

申请号：US15047271

申请日：2016-02-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Akhilesh Gautam ,  Randy W. Mann ,  William McMahon ,  Yoann Mamy Randriamihaja ,  Yuncheng Song

IPC: G11C11/00 ,  G11C29/52 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C29/52 ,  G11C7/04 ,  G11C11/412 ,  G11C11/419

Abstract: We disclose methods, apparatus, and systems for improving semiconductor device writeability through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS through the array VCS driver.