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    Method to identify extrinsic SRAM bits for failure analysis based on fail count voltage response
    5.
    发明授权
    Method to identify extrinsic SRAM bits for failure analysis based on fail count voltage response 有权
    基于故障计数电压响应来识别用于故障分析的外部SRAM位的方法

    公开(公告)号：US09548136B2

    公开(公告)日：2017-01-17

    申请号：US14664959

    申请日：2015-03-23

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Vivek Joshi ,  Sriram Balasubramanian ,  Chad Weintraub ,  Yoann Mamy Randriamihaja ,  William McMahon

    IPC: G11C29/00 ,  G11C29/04 ,  G11C11/419

    CPC classification number: G11C29/04 ,  G11C11/412 ,  G11C11/419 ,  G11C29/56008

    Abstract: A method and an apparatus for identifying non-intrinsic defect bits from a population of failing bits for failure analysis to characterize the extrinsic failure mechanisms is provided. Embodiments include performing a failure mode test on a bank of a memory array at different low VDD; determining optimal bank size to observe plateaus of fail counts; determining fail counts of the bank at each different low VDD; determining a plateau of the fail counts; determining whether the plateau represents extrinsic bits of the bank; and submitting the extrinsic bits for root cause analysis.

    Abstract translation: 提供了一种用于从用于故障分析的故障位群体中识别非本征缺陷位以表征外在故障机制的方法和装置。 实施例包括在不同的低VDD下对存储器阵列进行故障模式测试; 确定最佳银行规模以观察失败计数的平稳度; 在每个不同的低VDD处确定存储体的故障计数; 确定失败计数的高原; 确定平台是否代表银行的外在位; 并提交根本原因分析的外在位。

    METHODS, APPARATUS AND SYSTEM FOR SCREENING PROCESS SPLITS FOR TECHNOLOGY DEVELOPMENT
    6.
    发明申请
    METHODS, APPARATUS AND SYSTEM FOR SCREENING PROCESS SPLITS FOR TECHNOLOGY DEVELOPMENT 有权
    用于筛选技术开发过程分析的方法，装置和系统

    公开(公告)号：US20150346271A1

    公开(公告)日：2015-12-03

    申请号：US14288278

    申请日：2014-05-27

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Suresh Uppal ,  Andreas Kerber ,  William McMahon

    IPC: G01R31/26 ,  G01R31/12

    CPC classification number: G01R31/129 ,  G01R31/2607 ,  G01R31/2623 ,  G01R31/2642 ,  G01R31/2874

    Abstract: At least one method and system disclosed herein involves performing a time-dependent dielectric breakdown (TDDB) test and a bias temperature instability (BTI) test on a device. A device having at least one transistor and at least one dielectric layer is provided. A test signal is provided for performing a TDDB test and a BTI test on the device. The TDDB test and the BTI test are performed substantially simultaneously on the device based upon the test signal. The data relating to a breakdown of the dielectric layer and at least one characteristic of the transistor based upon the TDDB test and the BTI test is acquired, stored, and/or transmitted.

    Abstract translation: 本文公开的至少一种方法和系统涉及在器件上执行时间依赖介电击穿（TDDB）测试和偏置温度不稳定性（BTI）测试。 提供具有至少一个晶体管和至少一个电介质层的器件。 提供测试信号用于在设备上执行TDDB测试和BTI测试。 基于测试信号，在设备上基本上同时执行TDDB测试和BTI测试。 获取，存储和/或发送与介电层的击穿和基于TDDB测试和BTI测试的晶体管的至少一个特性相关的数据。

    WAFER TEST STRUCTURES AND METHODS OF PROVIDING WAFER TEST STRUCTURES
    9.
    发明申请
    WAFER TEST STRUCTURES AND METHODS OF PROVIDING WAFER TEST STRUCTURES 有权
    WAFER测试结构和提供波形测试结构的方法

    公开(公告)号：US20160025805A1

    公开(公告)日：2016-01-28

    申请号：US14337290

    申请日：2014-07-22

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Suresh UPPAL ,  Randy W. MANN ,  William McMahon

    IPC: G01R31/28 ,  H01L21/66 ,  H01L23/525

    CPC classification number: G01R31/2884 ,  G01R31/2644 ,  H01L22/14 ,  H01L22/34 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Wafer test structures and methods of providing wafer test structures are described. The methods include: fabricating multiple test devices and multiple fuse devices on the wafer, each test device having a respective fuse device associated therewith, which open circuits upon failure of the test device; and fabricating a selection circuit operative to selectively connect one test device to a sense contact pad, and the other test devices to a stress contact pad. The selection circuit facilitates sensing one or more electrical signals of the one test device by electrical contact with the sense contact pad, while stress testing the other test devices by electrical contact with the stress contact pad. In one embodiment, each test device has respective first and second switch devices, operative to selectively electrically connect the test device to the sense or stress contact pads. In another embodiment, the method includes wafer testing using the test structure.

    Abstract translation: 描述了晶片测试结构和提供晶片测试结构的方法。 这些方法包括：在晶片上制造多个测试装置和多个保险丝装置，每个测试装置具有与其相关联的相应的熔丝装置，其在测试装置故障时断开电路; 以及制造选择电路，其操作以选择性地将一个测试装置连接到感测触点焊盘，并且将其它测试装置连接到应力接触焊盘。 选择电路通过与感测接触焊盘的电接触便于感测一个测试装置的一个或多个电信号，同时通过与应力接触焊盘电接触来测试其它测试装置。 在一个实施例中，每个测试装置具有相应的第一和第二开关装置，其可操作以选择性地将测试装置电连接到感测或应力接触垫。 在另一个实施例中，该方法包括使用测试结构的晶片测试。

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