Invention Grant
- Patent Title: Bump-on-trace interconnection structure for flip-chip packages
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Application No.: US13658895Application Date: 2012-10-24
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Publication No.: US09917035B2Publication Date: 2018-03-13
- Inventor: Yu-Jen Tseng , Yen-Liang Lin , Tin-Hao Kuo , Chen-Shien Chen , Mirng-Ji Lii
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: H01L23/488
- IPC: H01L23/488 ; H01L23/00

Abstract:
A bump-on-trace interconnection structure utilizing a lower volume solder joint for joining a conductive metal pillar and a metal line trace includes a conductive metal pillar having a bonding surface having a width WP and a metal line trace, provided on a package substrate, having a top surface with a width WT, where WP is greater than WT. The solder joint is bonded to the bonding surface by wetting across the width WP and bonded predominantly only to the top surface of the metal line trace by wetting predominantly only to the top surface across the width WT.
Public/Granted literature
- US20140110847A1 BUMP-ON-TRACE INTERCONNECTION STRUCTURE FOR FLIP-CHIP PACKAGES Public/Granted day:2014-04-24
Information query
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