Invention Grant
- Patent Title: Critical dimension control for double patterning process
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Application No.: US14954380Application Date: 2015-11-30
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Publication No.: US09934985B2Publication Date: 2018-04-03
- Inventor: Che-Cheng Chang , Chih-Han Lin , Horng-Huei Tseng
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/311 ; H01L29/66 ; H01L21/8238 ; H01L21/8234
Abstract:
In a method for manufacturing a semiconductor device, a dummy gate layer and a hard mask layer are sequentially formed on a substrate. A first doped portion is formed in the dummy gate layer, and has an etching selectivity with respect to the other portion of the dummy gate layer. Etching masks are formed on portions of the hard mask layer. The hard mask layer and the dummy gate layer are etched to pattern the first doped portion and the other portion of the dummy gate layer into first dummy gates and second dummy gates. The first dummy gates and the second dummy gates have different widths. A dielectric layer is formed to peripherally enclose each of the first dummy gates and each of the second dummy gates. The first dummy gates and the second dummy gates are replaced with first metal gates and second metal gates.
Public/Granted literature
- US20170154886A1 CRITICAL DIMENSION CONTROL FOR DOUBLE PATTERNING PROCESS Public/Granted day:2017-06-01
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