公开(公告)号：US11948835B2

公开(公告)日：2024-04-02

申请号：US17230701

申请日：2021-04-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Che-Cheng Chang ,  Chih-Han Lin

IPC分类号： H01L21/768 ,  H01L23/485 ,  H01L23/528

CPC分类号： H01L21/76831 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76877 ,  H01L23/528 ,  H01L21/76804 ,  H01L23/485

摘要： A device comprises a first metal structure, a dielectric structure, a dielectric residue, and a second metal structure. The dielectric structure is over the first metal structure. The dielectric structure has a stepped sidewall structure. The stepped sidewall structure comprises a lower sidewall and an upper sidewall laterally set back from the lower sidewall. The dielectric residue is embedded in a recessed region in the lower sidewall of the stepped sidewall structure of the dielectric structure. The second metal structure extends through the dielectric structure to the first metal structure.

公开(公告)号：US11894277B2

公开(公告)日：2024-02-06

申请号：US17869590

申请日：2022-07-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Yao Lin ,  Chih-Han Lin ,  Shu-Uei Jang ,  Ya-Yi Tsai ,  Shu-Yuan Ku

IPC分类号： H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L21/823864 ,  H01L21/28123 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0924 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66545

摘要： A device includes a semiconductor substrate and a first gate stack over the semiconductor substrate, the first gate stack being between a first gate spacer and a second gate spacer. The device further includes a second gate stack over the semiconductor substrate between the first gate spacer and the second gate spacer and a dielectric material separating the first gate stack from the second gate stack. The dielectric material is at least partially between the first gate spacer and the second gate spacer, a first width of an upper portion of the dielectric material is greater than a second width of a lower portion of the dielectric material, and a third width of an upper portion of the first gate spacer is less than a fourth width of a lower portion of the first gate spacer.

公开(公告)号：US11854962B2

公开(公告)日：2023-12-26

申请号：US17106766

申请日：2020-11-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Che-Cheng Chang ,  Chih-Han Lin

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/288 ,  H01L23/532 ,  H01L21/027 ,  H01L21/321 ,  H01L29/06

CPC分类号： H01L23/5226 ,  H01L21/0276 ,  H01L21/2885 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/088 ,  H01L21/3212 ,  H01L21/7684 ,  H01L29/0649

摘要： A semiconductor device includes a substrate, a bottom etch stop layer over the substrate, a middle etch stop layer over the bottom etch stop layer, and a top etch stop layer over the middle etch stop layer. The top, middle, and bottom etch stop layers include different material compositions from each other. The semiconductor device further includes a dielectric layer over the top etch stop layer and a via extending through the dielectric layer and the top, middle, and bottom etch stop layers. The via has a first sidewall in contact with the dielectric layer and slanted inwardly from top to bottom towards a center of the via and a second sidewall in contact with the bottom etch stop layer and slanted outwardly from top to bottom away from the center of the via.

公开(公告)号：US11837649B2

公开(公告)日：2023-12-05

申请号：US16939943

申请日：2020-07-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Yao Lin ,  Chih-Han Lin

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L29/66545 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/785

摘要： A method includes forming an active channel region, forming a dummy channel region, forming a first gate dielectric layer over the active channel region, forming a second gate dielectric layer over the dummy channel region, removing the second gate dielectric layer from the dummy channel region, forming a gate isolation region over and contacting the dummy channel region, and forming a first gate stack and a second gate stack. The first gate stack is on the active channel region. The gate isolation region separates the first gate stack from the second gate stack.

公开(公告)号：US11784055B2

公开(公告)日：2023-10-10

申请号：US17692824

申请日：2022-03-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

IPC分类号： H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L23/31 ,  H01L29/66

CPC分类号： H01L21/3081 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/785 ,  H01L23/3157

摘要： A method includes following steps. A substrate is etched using a hard mask as an etch mask to form a fin. A bottom anti-reflective coating (BARC) layer is over the fin. A recess is formed in the BARC layer to expose a first portion of the hard mask. A protective coating layer is formed at least on a sidewall of the recess in the BARC layer. A first etching step is performed to remove the first portion of the hard mask to expose a first portion of the fin, while leaving a second portion of the fin covered under the protective coating layer and the BARC layer. A second etching step is performed to lower a top surface of the first portion of the fin to below a top surface of the second portion of the fin.

公开(公告)号：US11769821B2

公开(公告)日：2023-09-26

申请号：US17101291

申请日：2020-11-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Ping Chen ,  Kuei-Yu Kao ,  Shih-Yao Lin ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/66795 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/7851 ,  H01L2029/7858

摘要： A device includes a fin protruding from a semiconductor substrate; a gate stack over and along a sidewall of the fin; a gate spacer along a sidewall of the gate stack and along the sidewall of the fin; an epitaxial source/drain region in the fin and adjacent the gate spacer; and a corner spacer between the gate stack and the gate spacer, wherein the corner spacer extends along the sidewall of the fin, wherein a first region between the gate stack and the sidewall of the fin is free of the corner spacer, wherein a second region between the gate stack and the gate spacer is free of the corner spacer.

公开(公告)号：US11715779B2

公开(公告)日：2023-08-01

申请号：US17682604

申请日：2022-02-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Yao Lin ,  Chih-Chung Chiu ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin

IPC分类号： H01L29/423 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L21/3065 ,  H01L27/088 ,  H01L29/06

CPC分类号： H01L29/42392 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/66795 ,  H01L27/088

摘要： The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.

公开(公告)号：US20230154800A1

公开(公告)日：2023-05-18

申请号：US18157352

申请日：2023-01-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Che-Cheng Chang ,  Chih-Han Lin ,  Jr-Jung Lin

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L21/823481 ,  H01L29/66545 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823468

摘要： A semiconductor device includes a substrate, a fin protruding from the substrate, and a gate stack over the substrate and engaging the fin. The fin having a first end and a second end. The semiconductor device also includes a dielectric layer abutting the first end of the fin and spacer features disposed on sidewalls of the gate stack and on a top surface of the dielectric layer.

公开(公告)号：US20220359709A1

公开(公告)日：2022-11-10

申请号：US17813839

申请日：2022-07-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC分类号： H01L29/66 ,  H01L29/78

摘要： A method includes forming a dummy gate electrode on a semiconductor region, forming a first gate spacer on a sidewall of the dummy gate electrode, and removing an upper portion of the first gate spacer to form a recess, wherein a lower portion of the first gate spacer remains, filling the recess with a second gate spacer, removing the dummy gate electrode to form a trench, and forming a replacement gate electrode in the trench.

公开(公告)号：US20220328356A1

公开(公告)日：2022-10-13

申请号：US17808709

申请日：2022-06-24

申请人： Taiwan Semiconductor Manufacturing Co, Ltd.

发明人： Che-Cheng Chang ,  Chang-Yin Chen ,  Jr-Jung Lin ,  Chih-Han Lin ,  Yung-Jung Chang

IPC分类号： H01L21/8234 ,  H01L27/12 ,  H01L21/84 ,  H01L27/088 ,  H01L21/3213 ,  H01L29/78

摘要： Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.