Invention Grant
- Patent Title: Control of warpage using ABF GC cavity for embedded die package
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Application No.: US14491892Application Date: 2014-09-19
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Publication No.: US09941219B2Publication Date: 2018-04-10
- Inventor: Digvijay A. Rorane , Ian En Yoon Chin , Daniel N. Sobieski
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L21/66 ; H01L23/00 ; H01L21/50 ; H01L23/498 ; H01L23/31

Abstract:
Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.
Public/Granted literature
- US20160086894A1 CONTROL OF WARPAGE USING ABF GC CAVITY FOR EMBEDDED DIE PACKAGE Public/Granted day:2016-03-24
Information query
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