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    CONTROL OF WARPAGE USING ABF GC CAVITY FOR EMBEDDED DIE PACKAGE
    1.
    发明申请
    CONTROL OF WARPAGE USING ABF GC CAVITY FOR EMBEDDED DIE PACKAGE 有权
    使用ABF GC CAVITY进行嵌入式包装的控制

    公开(公告)号：US20160086894A1

    公开(公告)日：2016-03-24

    申请号：US14491892

    申请日：2014-09-19

    Applicant: Intel Corporation

    Inventor： DIGVIJAY A. RORANE ,  Ian En Yoon Chin ,  Daniel N. Sobieski

    IPC: H01L23/00 ,  H01L21/50 ,  H01L23/48

    CPC classification number: H01L23/562 ,  H01L21/50 ,  H01L23/3121 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2924/18162 ,  H01L2924/3511

    Abstract: Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.

    Abstract translation: 实施例包括半导体器件封装和形成这种封装的方法。 在一个实施例中，包装可以包括具有通过模头侧加强层形成的腔的模头侧加强层。 具有第一侧和包括器件侧的相对的第二侧的管芯可以定位在腔中，其中管芯的第一侧与模具侧加强层的第一侧基本上共面。 在一个实施例中，积聚结构可以联接到管芯的第二侧。 实施例包括包含图案化导电材料和绝缘材料的多个交替层的堆积结构。

    Control of warpage using ABF GC cavity for embedded die package
    3.
    发明授权
    Control of warpage using ABF GC cavity for embedded die package 有权

    公开(公告)号：US11322457B2

    公开(公告)日：2022-05-03

    申请号：US16849707

    申请日：2020-04-15

    Applicant: Intel Corporation

    Inventor： Digvijay A. Raorane ,  Ian En Yoon Chin ,  Daniel N. Sobieski

    IPC: H01L23/31 ,  H01L23/00 ,  H01L21/50 ,  H01L23/498

    Abstract: Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.

    Control of warpage using ABF GC cavity for embedded die package
    4.
    发明授权
    Control of warpage using ABF GC cavity for embedded die package 有权

    公开(公告)号：US10658307B2

    公开(公告)日：2020-05-19

    申请号：US15948958

    申请日：2018-04-09

    Applicant: Intel Corporation

    Inventor： Digvijay A. Rorane ,  Ian En Yoon Chin ,  Daniel N. Sobieski

    IPC: H01L21/76 ,  H01L23/00 ,  H01L21/50 ,  H01L23/498 ,  H01L23/31

    Abstract: Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.

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