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公开(公告)号：US09941054B2
公开(公告)日：2018-04-10
申请号：US15214390
申请日：2016-07-19
申请人： Intel Corporation
IPC分类号： H05K1/09 , H01G4/33 , H01L21/48 , H01L23/498 , H05K1/11 , H05K1/18 , H05K3/00 , H05K3/18 , H05K3/46 , H05K1/16
CPC分类号： H01G4/33 , H01L21/4857 , H01L23/49822 , H01L23/49827 , H01L2224/16225 , H01L2924/15311 , H05K1/09 , H05K1/115 , H05K1/162 , H05K1/185 , H05K3/0017 , H05K3/188 , H05K3/4644 , H05K3/467 , H05K2201/10015
摘要： An embedded thin film capacitor and methods of its fabrication are disclosed. The embedded thin film capacitor includes two conductive plates separated by a dielectric layer. In embodiments, the capacitor is enclosed within a package substrate. A method of forming the embedded thin film capacitor includes forming a first insulating layer on a bottom plate and a first trace. A first opening is then formed in a first insulating layer to expose a first region of a bottom plate. An adhesive layer is then formed on the first insulating layer and on top of the exposed first region of the bottom plate. A second opening is formed through the insulating layer and the first insulating layer to expose a second region of the bottom plate. A top plate is formed within the first opening and a via is formed within the second opening.
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公开(公告)号：US09633938B2
公开(公告)日：2017-04-25
申请号：US14866491
申请日：2015-09-25
申请人： INTEL CORPORATION
IPC分类号： H01L23/52 , H01L23/498 , H01L23/00 , H01L21/02 , H01L21/32 , H01L21/768 , H01L21/3205 , H01L21/285
CPC分类号： H01L23/49838 , H01L21/02263 , H01L21/28556 , H01L21/32 , H01L21/3205 , H01L21/4857 , H01L21/768 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/49894 , H01L24/11 , H01L24/16 , H01L2224/16227 , H01L2924/1205 , H05K1/162
摘要： A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).
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公开(公告)号：US10658307B2
公开(公告)日：2020-05-19
申请号：US15948958
申请日：2018-04-09
申请人： Intel Corporation
IPC分类号： H01L21/76 , H01L23/00 , H01L21/50 , H01L23/498 , H01L23/31
摘要： Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.
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公开(公告)号：US09941219B2
公开(公告)日：2018-04-10
申请号：US14491892
申请日：2014-09-19
申请人： Intel Corporation
IPC分类号： H01L23/495 , H01L21/66 , H01L23/00 , H01L21/50 , H01L23/498 , H01L23/31
CPC分类号： H01L23/562 , H01L21/50 , H01L23/3121 , H01L23/498 , H01L23/49816 , H01L23/49822 , H01L24/19 , H01L24/20 , H01L2224/04105 , H01L2224/12105 , H01L2224/18 , H01L2924/18162 , H01L2924/3511
摘要： Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.
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公开(公告)号：US10103037B2
公开(公告)日：2018-10-16
申请号：US14273754
申请日：2014-05-09
申请人： Intel Corporation
发明人： Aleksandar Aleksov , Dilan Seneviratne , Charavana K. Gurumurthy , Ching-Ping J. Shen , Daniel N. Sobieski
摘要： Microelectronic systems encapsulated in a stretchable/flexible material, which is skin/bio-compatible and able to withstand environmental conditions. In one embodiment of the present description, the microelectronic system includes a microelectronic device that is substantially encapsulated in a non-permeable encapsulant, such as, butyl rubbers, ethylene propylene rubbers, fluoropolymer elastomers, or combinations thereof. In another embodiment, the microelectronic system includes a microelectronic device that is substantially encapsulated in a permeable encapsulant, such as polydimethylsiloxane, wherein a non-permeable encapsulant substantially encapsulates the permeable encapsulant.
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6.发明授权Thin film based electromagnetic interference shielding with BBUL/coreless packages 有权基于薄膜的电磁干扰屏蔽与BBUL /无芯封装公开(公告)号：US09232686B2
公开(公告)日：2016-01-05
申请号：US14227929
申请日：2014-03-27
申请人： INTEL CORPORATION
CPC分类号： H05K3/007 , C23C14/14 , H01L21/4857 , H01L21/561 , H01L21/568 , H01L23/3128 , H01L23/49811 , H01L23/49822 , H01L23/5389 , H01L23/552 , H01L24/19 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/19 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2924/1815 , H01L2924/18162 , H05K1/0219 , H05K1/185 , H05K3/02 , H05K3/30 , H05K3/4682 , H05K2201/0715 , H05K2203/1469 , H05K2203/308 , H01L2224/83 , H01L2224/82 , H01L2224/83005
摘要： An apparatus including a die including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the die, the build-up carrier including a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die; and an interference shield including a conductive material disposed on the die and a portion of the build-up carrier. The apparatus may be connected to a printed circuit board. A method including forming a build-up carrier adjacent a device side of a die including a plurality of alternating layers of patterned conductive material and insulating material; and forming a interference shield on a portion of the build-up carrier.
摘要翻译： 一种包括模具的装置，包括具有限定模具的厚度的接触点和侧壁的装置侧; 耦合到管芯的积聚载体，所述堆积载体包括多个图案化导电材料和绝缘材料的交替层，其中图案化导电材料层中的至少一层耦合到 死; 以及包括设置在管芯上的导电材料和积聚载体的一部分的干涉屏蔽。 该装置可以连接到印刷电路板。 一种方法，包括在包括图案化导电材料和绝缘材料的多个交替层的模具的器件侧附近形成堆积载体; 以及在积聚载体的一部分上形成干涉屏蔽。
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公开(公告)号：US12009318B2
公开(公告)日：2024-06-11
申请号：US17714944
申请日：2022-04-06
申请人： Intel Corporation
IPC分类号： H01L23/49 , H01L21/50 , H01L23/00 , H01L23/498 , H01L23/31
CPC分类号： H01L23/562 , H01L21/50 , H01L23/498 , H01L23/49816 , H01L23/49822 , H01L24/19 , H01L24/20 , H01L23/3121 , H01L2224/04105 , H01L2224/12105 , H01L2224/18 , H01L2924/18162 , H01L2924/3511
摘要： Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.
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公开(公告)号：US11322457B2
公开(公告)日：2022-05-03
申请号：US16849707
申请日：2020-04-15
申请人： Intel Corporation
IPC分类号： H01L23/31 , H01L23/00 , H01L21/50 , H01L23/498
摘要： Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.
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公开(公告)号：US10375832B2
公开(公告)日：2019-08-06
申请号：US14956214
申请日：2015-12-01
申请人： Intel Corporation
IPC分类号： H05K1/02 , H05K1/18 , H05K3/00 , H05K3/02 , H05K3/30 , H05K3/46 , C23C14/14 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/498 , H01L23/538 , H01L23/552
摘要： An apparatus including a die including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the die, the build-up carrier including a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die; and an interference shield including a conductive material disposed on the die and a portion of the build-up carrier. The apparatus may be connected to a printed circuit board. A method including forming a build-up carrier adjacent a device side of a die including a plurality of alternating layers of patterned conductive material and insulating material; and forming a interference shield on a portion of the build-up carrier.
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10.发明申请公开(公告)号：US20160183361A1
公开(公告)日：2016-06-23
申请号：US14773108
申请日：2014-12-09
申请人： Intel Corporation
CPC分类号： C22C9/00 , C22C27/04 , H01L23/12 , H01L23/49 , H01L23/49866 , H01L2224/0401 , H01L2224/131 , H01L2224/16227 , H01L2224/16238 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/81203 , H01L2224/81205 , H01L2224/81815 , H01L2924/15311 , H01L2924/3511 , H01L2924/00014 , H01L2924/014 , H01L2924/0665
摘要： Microelectronic substrates having copper alloy conductive routes to reduce warpage due to differing coefficient of thermal expansion of the components used to form the microelectronic substrates. In one embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper and an alloying metal of tungsten, molybdenum, or a combination thereof. In another embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper, an alloying metal of tungsten, molybdenum, or a combination thereof, and a co-deposition metal of nickel, cobalt, iron, or a combination thereof. In still another embodiment, the copper alloy conductive routes may have copper concentrations which are graded therethrough, which may enable better pattern formation during a subtractive etching process used to form the copper alloy conductive routes.
摘要翻译： 具有铜合金导电路径的微电子基板，以减少由于用于形成微电子基板的部件的不同的热膨胀系数而引起的翘曲。 在一个实施例中，微电子衬底的导电路径可以包括铜和钨，钼或其组合的合金金属的合金。 在另一个实施例中，微电子衬底的导电路径可以包括铜，钨的合金金属，钼或其组合的合金，以及镍，钴，铁或它们的组合的共沉积金属。 在另一个实施例中，铜合金导电路线可以具有通过其分级的铜浓度，这可以在用于形成铜合金导电路径的减去蚀刻工艺期间实现更好的图案形成。
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