Invention Grant
- Patent Title: Bias circuitry for depletion mode amplifiers
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Application No.: US15175610Application Date: 2016-06-07
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Publication No.: US09960740B2Publication Date: 2018-05-01
- Inventor: John P. Bettencourt , Alan J. Bielunis , Istvan Rodriguez , Zhaoyang C. Wang
- Applicant: Raytheon Company
- Applicant Address: US MA Waltham
- Assignee: Raytheon Company
- Current Assignee: Raytheon Company
- Current Assignee Address: US MA Waltham
- Agency: Daly, Crowley, Mofford & Durkee, LLP
- Main IPC: H03F3/04
- IPC: H03F3/04 ; H03F3/195 ; H03F3/193 ; H03F3/72 ; H03F3/213 ; H03F1/30

Abstract:
A circuit having an amplifier, comprising: a depletion mode transistor having a source electrode coupled to a reference potential; a drain electrode coupled to a potential more positive than the reference potential; and a gate electrode for coupling to an input signal. The circuit includes a bias circuit, comprising: a current source; and biasing circuitry coupled to the current source and between the potential more positive than the reference potential and a potential more negative than the reference potential. A control circuit is connected to the current source for controlling the amount of current produced by the current source to the biasing circuitry.
Public/Granted literature
- US20160373074A1 Bias Circuitry For Depletion Mode Amplifiers Public/Granted day:2016-12-22
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