Invention Grant
- Patent Title: Method for managing a fail bit line of a memory plane of a non volatile memory and corresponding memory device
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Application No.: US15140997Application Date: 2016-04-28
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Publication No.: US09984770B2Publication Date: 2018-05-29
- Inventor: Francesco La Rosa , Gineuve Alieri
- Applicant: STMicroelectronics (Rousset) SAS
- Applicant Address: FR Rousset
- Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee Address: FR Rousset
- Agency: Slater Matsil, LLP
- Priority: FR1561729 20151202
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G11C29/52 ; G06F11/10 ; H03M13/29 ; G11C29/04

Abstract:
A method can be used for managing the operation of a non-volatile memory equipped with a system for correction of a single error and for detection of a double error. In the case of the detection of a defective bit line of the memory plane, a redundant bit line is assigned and the values of the bits of the memory cells of the defective line are copied into the memory cells of the redundant line and are inverted in the case of the detection of double errors by the system, or corrected by the system in the presence of single errors.
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