- 专利标题: Mechanism for instruction set based thread execution of a plurality of instruction sequencers
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申请号: US13843164申请日: 2013-03-15
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公开(公告)号: US09990206B2公开(公告)日: 2018-06-05
- 发明人: Hong Wang , John Shen , Edward Grochowski , Richard Hankins , Gautham Chinya , Bryant Bigbee , Shivnandan Kaushik , Xiang Chris Zou , Per Hammarlund , Scott Dion Rodgers , Xinmin Tian , Anil Aggawal , Prashant Sethi , Baiju Patel , James Held
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: INTEL CORPORATION
- 当前专利权人: INTEL CORPORATION
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Nicholson De Vos Webster & Elliott LLP
- 主分类号: G06F9/46
- IPC分类号: G06F9/46 ; G06F9/38 ; G06F9/30 ; G06F9/48
摘要:
In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.
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