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公开(公告)号：US20200242046A1
公开(公告)日：2020-07-30
申请号：US16560213
申请日：2019-09-04
申请人： Intel Corporation
发明人： Edward Grochowski , Julio Gago , Roger Gramunt , Roger Espasa , Rolf Kassa
IPC分类号： G06F12/1009 , G06F12/0864 , G06F12/14 , G06F12/1027
摘要： A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.
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公开(公告)号：US20210374069A1
公开(公告)日：2021-12-02
申请号：US17404770
申请日：2021-08-17
申请人： Intel Corporation
发明人： Edward Grochowski , Julio Gago , Roger Gramunt , Roger Espasa , Rolf Kassa
IPC分类号： G06F12/1009 , G06F12/1027 , G06F12/14 , G06F12/0864
摘要： A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.
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公开(公告)号：US10585667B2
公开(公告)日：2020-03-10
申请号：US15900030
申请日：2018-02-20
申请人： Intel Corporation
发明人： Edward Grochowski , Hong Wang , John P. Shen , Perry H. Wang , Jamison D. Collins , James Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
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4.发明授权公开(公告)号：US09990206B2
公开(公告)日：2018-06-05
申请号：US13843164
申请日：2013-03-15
申请人： Intel Corporation
发明人： Hong Wang , John Shen , Edward Grochowski , Richard Hankins , Gautham Chinya , Bryant Bigbee , Shivnandan Kaushik , Xiang Chris Zou , Per Hammarlund , Scott Dion Rodgers , Xinmin Tian , Anil Aggawal , Prashant Sethi , Baiju Patel , James Held
CPC分类号： G06F9/3867 , G06F9/30003 , G06F9/30043 , G06F9/3005 , G06F9/3009 , G06F9/30145 , G06F9/3017 , G06F9/30174 , G06F9/3851 , G06F9/4843 , G06F9/4881
摘要： In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.
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公开(公告)号：US10445245B2
公开(公告)日：2019-10-15
申请号：US15384067
申请日：2016-12-19
申请人： Intel Corporation
发明人： Edward Grochowski , Julio Gago , Roger Gramunt , Roger Espasa , Rolf Kassa
IPC分类号： G06F12/1009 , G06F12/1027 , G06F12/14 , G06F12/0864
摘要： A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.
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公开(公告)号：US10445244B2
公开(公告)日：2019-10-15
申请号：US15384054
申请日：2016-12-19
申请人： Intel Corporation
发明人： Edward Grochowski , Julio Gago , Roger Gramunt , Roger Espasa , Rolf Kassa
IPC分类号： G06F12/1009 , G06F12/1027 , G06F12/14 , G06F12/0864
摘要： A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.
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公开(公告)号：US20180321936A1
公开(公告)日：2018-11-08
申请号：US15943609
申请日：2018-04-02
申请人： Intel Corporation
发明人： Edward Grochowski , Hong Wang , John P. Shen , Perry H. Wang , Jamison D. Collins , James Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
CPC分类号： G06F9/30003 , G06F9/30087 , G06F9/3009 , G06F9/30101 , G06F9/3013 , G06F9/384 , G06F9/3851
摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
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公开(公告)号：US09934155B2
公开(公告)日：2018-04-03
申请号：US13722485
申请日：2012-12-20
申请人： Intel Corporation
发明人： Edward Grochowski , Julio Gago , Roger Gramunt , Roger Espasa , Rolf Kassa
IPC分类号： G06F12/10 , G06F12/14 , G06F12/1009 , G06F12/1027 , G06F12/109
CPC分类号： G06F12/1009 , G06F12/0864 , G06F12/1027 , G06F12/109 , G06F12/145 , G06F2212/152 , G06F2212/6032 , G06F2212/652 , G06F2212/657 , G06F2212/68
摘要： A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.
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