Invention Application
WO2003019399A1 A MULTIPROCESSOR INFRASTRUCTURE FOR PROVIDING FLEXIBLE BANDWIDTH ALLOCATION VIA MULTIPLE INSTANTIATIONS OF SEPARATE DATA BUSES, CONTROL BUSES AND SUPPORT MECHANISMS
审中-公开
用于通过多种数据总线，控制总线和支持机制的多次实时提供灵活带宽分配的多处理器基础设施
- Patent Title: A MULTIPROCESSOR INFRASTRUCTURE FOR PROVIDING FLEXIBLE BANDWIDTH ALLOCATION VIA MULTIPLE INSTANTIATIONS OF SEPARATE DATA BUSES, CONTROL BUSES AND SUPPORT MECHANISMS
- Patent Title (中): 用于通过多种数据总线，控制总线和支持机制的多次实时提供灵活带宽分配的多处理器基础设施
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Application No.: PCT/US2002/027430Application Date: 2002-08-27
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Publication No.: WO2003019399A1Publication Date: 2003-03-06
- Inventor: ROSENBLUTH, Mark , WOLRICH, Gilbert , BERNSTEIN, Debra , WILDE, Myles , ADILETTA, Matthew
- Applicant: INTEL CORPORATION
- Applicant Address: 2200 Mission College Boulevard, Santa Clara, CA 95052 US
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: 2200 Mission College Boulevard, Santa Clara, CA 95052 US
- Agency: HARRIS, Scott, C.
- Priority: US60/315,144 200108027; US10/212,944 20020805
- Main IPC: G06F13/40
- IPC: G06F13/40
Abstract:
A bus mechanism to control information exchanges between bus masters and bus targets over a bus structure that includes separate command, push and pull data buses. Commands are generated by bus masters and are interpreted by bus targets on a per-target basis. Each bus target controls the servicing of a command intended for such target by controlling the transfer of push data over the push bus to a bus master specified in the command as a destination, for a push operation type, and by controlling the transfer of pull data over the pull bus to the target from a bus master specified in the command as a destination, for a pull operation type. Arbitration logic associated with each bus is used to control the flow of the information exchanges on that bus.
Information query
