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    INSTRUCTION-ASSISTED CACHE MANAGEMENT FOR EFFICIENT USE OF CACHE AND MEMORY
    4.
    发明申请
    INSTRUCTION-ASSISTED CACHE MANAGEMENT FOR EFFICIENT USE OF CACHE AND MEMORY 审中-公开
    指令性协调的高速缓存管理，以便有效地使用缓存和内存

    公开(公告)号：WO2007041145A1

    公开(公告)日：2007-04-12

    申请号：PCT/US2006/037631

    申请日：2006-09-26

    Applicant: INTEL CORPORATION ,  LAKSHMANAMURTHY, Sridhar ,  ROSENBLUTH, Mark

    Inventor： LAKSHMANAMURTHY, Sridhar ,  ROSENBLUTH, Mark

    IPC: G06F12/12 ,  G06F12/08

    CPC classification number: G06F9/30047 ,  G06F12/0804 ,  G06F12/0888 ,  G06F12/126

    Abstract: Instruction-assisted cache management for efficient use of cache and memory. Hints (e.g., modifiers) are added to read and write memory access instructions to identify the memory access is for temporal data. In view of such hints, alternative cache policy and allocation policies are implemented that minimize cache and memory access. Under one policy, a write cache miss may result in a write of data to a partial cache line without a memory read/write cycle to fill the remainder of the line. Under another policy, a read cache miss may result in a read from memory without allocating or writing the read data to a cache line. A cache line soft-lock mechanism is also disclosed, wherein cache lines may be selectably soft locked to indicate preference for keeping those cache lines over non-locked lines.

    Abstract translation: 指令辅助缓存管理，用于缓存和内存的高效使用。 添加提示（例如，修饰符）来读取和写入存储器访问指令以识别用于时间数据的存储器访问。 鉴于这样的提示，实现了使缓存和存储器访问最小化的替代高速缓存策略和分配策略。 在一个策略下，写入高速缓存未命中可能导致将数据写入部分高速缓存行而没有存储器读/写周期来填充该行的剩余部分。 在另一策略下，读高速缓存未命中可能导致从存储器的读取，而无需将读取的数据分配或写入高速缓存行。 还公开了一种高速缓存行软锁定机制，其中高速缓存行可以被可选地软锁定以指示将这些高速缓存行保持在非锁定行上的偏好。

    FREE LIST AND RING DATA STRUCTURE MANAGEMENT
    5.
    发明申请
    FREE LIST AND RING DATA STRUCTURE MANAGEMENT 审中-公开
    免费清单和环数据结构管理

    公开(公告)号：WO2004015525A2

    公开(公告)日：2004-02-19

    申请号：PCT/US2003/024345

    申请日：2003-08-04

    Applicant: INTEL CORPORATION

    Inventor： WOLRICH, Gilbert ,  SWEENEY, John ,  GUILFORD, James ,  ROSENBLUTH, Mark ,  BERNSTEIN, Debra

    IPC: G06F

    CPC classification number: H04L49/9047 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9031

    Abstract: A method of managing a free list and ring data structure, which may be used to store journaling information, by storing and modifying information describing a structure of the free list or ring data structure in a cache memory that may also be used to store information describing a structure of a queue of buffers.

    Abstract translation: 一种管理可用于存储日志信息的空闲列表和环形数据结构的方法，通过将描述自由列表或环形数据结构的结构的信息存储和修改，该高速缓冲存储器也可用于存储描述的信息 缓冲区队列的结构。

    REGISTERS FOR DATA TRANSFERS WITHIN A MULTITHREADED PROCESSOR
    9.
    发明申请
    REGISTERS FOR DATA TRANSFERS WITHIN A MULTITHREADED PROCESSOR 审中-公开
    在多处理器中进行数据传输的寄存器

    公开(公告)号：WO2003085517A1

    公开(公告)日：2003-10-16

    申请号：PCT/US2003/009478

    申请日：2003-03-27

    Applicant: INTEL CORPORATION (A DELAWARE CORPORATION)

    Inventor： WOLRICH, Gilbert ,  ROSENBLUTH, Mark ,  BERNSTEIN, Debra ,  ADILETTA, Matthew

    IPC: G06F9/30

    CPC classification number: G06F9/4843 ,  G06F9/30101 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3851

    Abstract: A system and method for employing registers for data transfer in multiple hardware contexts and programming engines to facilitate high performance data processing. The system and method includes a processor that includes programming engines with registers for transferring data from one of the registers residing in an executing programming engine to a subsequent one of the registers residing in an adjacent programming engine.

    Abstract translation: 一种用于在多个硬件上下文和编程引擎中采用用于数据传输的寄存器以便于高性能数据处理的系统和方法。 该系统和方法包括处理器，其包括具有寄存器的编程引擎，用于将驻留在执行编程引擎中的寄存器中的一个寄存器中的数据传送到驻留在相邻编程引擎中的后续寄存器中的寄存器。

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