公开(公告)号：WO2009012050A3

公开(公告)日：2009-01-22

申请号：PCT/US2008/068801

申请日：2008-06-30

Applicant: INTEL CORPORATION ,  GUERON, Shay ,  GOPAL, Vinodh ,  FEGHALI, Wajdi, K. ,  WOLRICH, Gilbert

Inventor： GUERON, Shay ,  GOPAL, Vinodh ,  FEGHALI, Wajdi, K. ,  WOLRICH, Gilbert

IPC: G06F7/52

Abstract: A technique of determining a message residue includes accessing a message and simultaneously determining a set of modular remainders with respect to a polynomial for different respective segments of the message. The technique also includes determining a modular remainder with respect to the polynomial for the message based on the set of modular remainders and a set of constants determined prior to accessing the message. The modular remainder with respect to the polynomial for the message is stored in a memory.

公开(公告)号：WO2008027734A1

公开(公告)日：2008-03-06

申请号：PCT/US2007/076147

申请日：2007-08-16

Applicant: INTEL CORPORATION ,  GOPAL, Vinodh ,  WOLRICH, Gilbert ,  CUTTER, Daniel ,  FEGHALI, Wajdi ,  OTTAVI, Robert, P.

Inventor： GOPAL, Vinodh ,  WOLRICH, Gilbert ,  CUTTER, Daniel ,  FEGHALI, Wajdi ,  OTTAVI, Robert, P.

IPC: G06F3/06 ,  G06F12/16

CPC classification number: G06F11/1076 ,  G06F2211/1054 ,  G06F2211/1057

Abstract: The present disclosure provides an apparatus and method for generating a Galois-field syndrome. One exemplary method may include loading a first data byte from a first storage device to a first register and loading a second data byte from a second storage device to a second register; ANDing the most significant bit (MSB) of the first data byte and a Galois-field polynomial to generate a first intermediate output; XORing each bit of the first intermediate output with the least significant bits (LSBs) of the first data byte to generate a second intermediate output; MUXing the second intermediate output with each bit of the first data byte to generate a third intermediate output; XORing each bit of the third intermediate output with each bit of the second data byte to generate at a fourth intermediate output; and generating a RAID Q syndrome based on, at least in part, the fourth intermediate output. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

Abstract translation: 本公开提供了一种用于产生伽罗瓦域综合征的装置和方法。 一个示例性方法可以包括将第一数据字节从第一存储设备加载到第一寄存器，并将第二数据字节从第二存储设备加载到第二寄存器; 将第一数据字节的最高有效位（MSB）和伽罗瓦域多项式进行比较以产生第一中间输出; 用第一数据字节的最低有效位（LSB）对第一中间输出的每个位进行异或，以产生第二中间输出; 将第二中间输出与第一数据字节的每个位进行多路复用以产生第三中间​​输出; 将第三中间输出的每个位与第二数据字节的每个位进行异或，以在第四中间输出处产生; 以及至少部分地基于第四中间输出产生RAID Q综合征。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

公开(公告)号：WO2006039183A3

公开(公告)日：2006-04-13

申请号：PCT/US2005/034010

申请日：2005-09-21

Applicant: INTEL CORPORATION ,  WOLRICH, Gilbert ,  ROSENBLUTH, Mark ,  ADILETTA, Matthew ,  WILKINSON, Hugh ,  NIELL, Jose ,  NARAYANAN, Rajagopal ,  JAIN, Sanjeev

Inventor： WOLRICH, Gilbert ,  ROSENBLUTH, Mark ,  ADILETTA, Matthew ,  WILKINSON, Hugh ,  NIELL, Jose ,  NARAYANAN, Rajagopal ,  JAIN, Sanjeev

IPC: G06F9/32

Abstract: Method and apparatus to support expansion of compute engine code space by sharing adjacent control stores using interleaved addressing schemes. Instructions corresponding to an original instruction thread are partitioned into multiple interleaved sequences that are stored in respective control stores. During thread execution, instructions are retrieved from the control stores in a repeated order based on the interleaving scheme. For example, in one embodiment two compute engines share two control stores. Thus, instructions for a given thread are sequentially loaded from the control stores in an alternating manner. In another embodiment, four control stores are shared by four compute engines. In this case, the instructions in a thread are interleave using four stores, and each store is accessed every fourth instruction in the code sequence. Schemes are also provided for handling branching operations to maintain synchronized access to the control stores.

公开(公告)号：WO2003019358A1

公开(公告)日：2003-03-06

申请号：PCT/US2002/027273

申请日：2002-08-27

Applicant: INTEL CORPORATION

Inventor： ROSENBLUTH, Mark ,  WOLRICH, Gilbert ,  BERNSTEIN, Debra

IPC: G06F9/38

CPC classification number: G06F9/3885 ,  G06F9/30098 ,  G06F9/30123 ,  G06F9/3851

Abstract: A mechanism in a multithreaded processor to allocate resources based on configuration information indicating how many threads are in use.

Abstract translation: 多线程处理器中基于配置信息分配资源的机制，该配置信息指示正在使用多少线程。

公开(公告)号：WO2010077904A3

公开(公告)日：2010-07-08

申请号：PCT/US2009/068168

申请日：2009-12-16

Applicant: INTEL CORPORATION ,  GOPAL, Vinodh ,  CLARK, Christopher, F. ,  WOLRICH, Gilbert ,  FEGHALI, Wajdi

Inventor： GOPAL, Vinodh ,  CLARK, Christopher, F. ,  WOLRICH, Gilbert ,  FEGHALI, Wajdi

IPC: H04L12/26 ,  G06F21/20

Abstract: Methods and apparatus to perform string matching for network packet inspection are disclosed. In some embodiments there is a set of string matching slice circuits, each slice circuit of the set being configured to perform string matching steps in parallel with other slice circuits. Each slice circuit may include an input window storing some number of bytes of data from an input data steam. The input window of data may be padded if necessary, and then multiplied by a polynomial modulo an irreducible Galois-field polynomial to generate a hash index. A storage location of a memory corresponding to the hash index may be accessed to generate a slice-hit signal of a set of H slice-hit signals. The slice-hit signal may be provided to an AND-OR logic array where the set of H slice-hit signals is logically combined into a match result.

公开(公告)号：WO2003098452A1

公开(公告)日：2003-11-27

申请号：PCT/US2003/013687

申请日：2003-05-02

Applicant: INTEL CORPORATION

Inventor： WOLRICH, Gilbert ,  ROSENBLUTH, Mark ,  BERNSTEIN, Debra ,  WILDE, Myles

IPC: G06F13/16

CPC classification number: G06F13/4234

Abstract: The invention features a method for transferring data to programming engines using multiple memory channels, parsing data over at most two channels in the memory channels, and establishing at most two logical states to signal completion of a memory transfer operation.

Abstract translation: 本发明的特征在于一种用于使用多个存储器信道将数据传送到编程引擎的方法，在存储器通道中最多两个通道解析数据，并且建立至多两个逻辑状态来信号完成存储器传送操作。

公开(公告)号：WO2003063018A2

公开(公告)日：2003-07-31

申请号：PCT/US2003/001578

申请日：2003-01-16

Applicant: INTEL CORPORATION (A DELAWARE CORPORATION)

Inventor： ADILETTA, Matthew ,  BERNSTEIN, Debra ,  WILDE, Myles ,  WOLRICH, Gilbert ,  ROSENBLUTH, Mark ,  WILKINSON, Hugh

IPC: G06F15/76

CPC classification number: G06F15/8053

Abstract: A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes a parallel processor that assigns system functions for processing data including programming engines that support multiple contexts arranged to provide a functional pipeline by a functional pipeline control unit that passes functional data among the programming engines.

Abstract translation: 一种用于在功能管线中采用多个硬件上下文和编程引擎的系统和方法，该功能管线被划分以便于高性能数据处理。 该系统和方法包括并行处理器，其分配用于处理数据的系统功能，所述系统功能包括支持多个上下文的编程引擎，所述编程引擎被布置为通过在所述编程引擎之间传递功能数据的功能流水线控制单元提供功能

公开(公告)号：WO2003019399A1

公开(公告)日：2003-03-06

申请号：PCT/US2002/027430

申请日：2002-08-27

Applicant: INTEL CORPORATION

Inventor： ROSENBLUTH, Mark ,  WOLRICH, Gilbert ,  BERNSTEIN, Debra ,  WILDE, Myles ,  ADILETTA, Matthew

IPC: G06F13/40

CPC classification number: G06F13/364 ,  G06F13/4004

Abstract: A bus mechanism to control information exchanges between bus masters and bus targets over a bus structure that includes separate command, push and pull data buses. Commands are generated by bus masters and are interpreted by bus targets on a per-target basis. Each bus target controls the servicing of a command intended for such target by controlling the transfer of push data over the push bus to a bus master specified in the command as a destination, for a push operation type, and by controlling the transfer of pull data over the pull bus to the target from a bus master specified in the command as a destination, for a pull operation type. Arbitration logic associated with each bus is used to control the flow of the information exchanges on that bus.

Abstract translation: 一种总线机制，用于通过总线结构控制总线主机和总线目标之间的信息交换，该总线结构包括单独的命令，推拉数据总线。 命令由公交车主人生成，并由每个目标的公交车目标解释。 每个总线目标通过控制通过推送总线将推送数据传送到作为目的地的命令中指定的总线主机，用于推送操作类型，并且通过控制拉动数据的传送来控制对该目标的命令的服务 通过从作为目的地的命令中指定的总线主机到目的地的拉取总线，用于拉动操作类型。 与每个总线相关联的仲裁逻辑用于控制该总线上的信息交换流。

公开(公告)号：WO2003019380A2

公开(公告)日：2003-03-06

申请号：PCT/US2002/027353

申请日：2002-08-27

Applicant: INTEL CORPORATION

Inventor： ROSENBLUTH, Mark ,  WOLRICH, Gilbert ,  BERNSTEIN, Debra

IPC: G06F12/00

CPC classification number: G06F9/30087 ,  G06F9/30021 ,  G06F9/3004 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3885

Abstract: Stored units of information related to packet processing are associated with identifiers, each of which is maintained as an entry in a Content Addressable Memory (CAM). Each entry includes status information associated with the information unit with which the identifier is associated. The status information is used to determine validity of the information unit with which the status information is associated.

Abstract translation: 与分组处理相关的信息的存储单元与标识符相关联，每个标识符被保持为内容可寻址存储器（CAM）中的条目。 每个条目包括与标识符相关联的信息单元相关联的状态信息。 状态信息用于确定状态信息与之相关联的信息单元的有效性。

公开(公告)号：WO2008121734A1

公开(公告)日：2008-10-09

申请号：PCT/US2008/058505

申请日：2008-03-27

Applicant: INTEL CORPORATION ,  GOPAL, Vinodh ,  WOLRICH, Gilbert ,  FEGHALI, Wajdi ,  OZTURK, Erdinc ,  YAP, Kirk S.

Inventor： GOPAL, Vinodh ,  WOLRICH, Gilbert ,  FEGHALI, Wajdi ,  OZTURK, Erdinc ,  YAP, Kirk S.

IPC: H04L9/14

CPC classification number: H04L9/0631 ,  G06F9/30007 ,  H04L2209/125

Abstract: The speed at which encrypt and decrypt operations may be performed in a general purpose processor is increased by providing a separate encrypt data path and decrypt data path. With separate data paths, each of the data paths may be individually optimized in order to reduce delays in a critical path. In addition, delays may be hidden in a non-critical last round.

Abstract translation: 可以通过提供单独的加密数据路径和解密数据路径来增加在通用处理器中执行加密和解密操作的速度。 利用单独的数据路径，可以单独优化每个数据路径以减少关键路径中的延迟。 此外，延迟可能隐藏在非关键的最后一轮。