Invention Application
WO2013052345A1 STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE
审中-公开
对于没有接线的组件，可以进行集成最小化以封装基板
- Patent Title: STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE
- Patent Title (中): 对于没有接线的组件，可以进行集成最小化以封装基板
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Application No.: PCT/US2012/057554Application Date: 2012-09-27
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Publication No.: WO2013052345A1Publication Date: 2013-04-11
- Inventor: CRISP, Richard, Dewitt , ZOHNI, Wael , HABA, Belgacem , LAMBRECHT, Frank
- Applicant: INVENSAS CORPORATION
- Applicant Address: 2702 Orchard Parkway San Jose, CA 95134 US
- Assignee: INVENSAS CORPORATION
- Current Assignee: INVENSAS CORPORATION
- Current Assignee Address: 2702 Orchard Parkway San Jose, CA 95134 US
- Agency: NEFF, Daryl, K. et al.
- Priority: US61/600,361 20120217; US61/542,488 20111003; US61/542,553 20111003; US13/439,286 20120404
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L25/065
Abstract:
A microelectronic package (100) can include a substrate (102) and a microelectronic element (130) having a face (134) and one or more columns (138, 139) of contacts (132) exposed thereat which face and are joined to corresponding contacts exposed at a surface (120) of the substrate. An axial plane (140) may intersect the face along a line in a first direction (142) and centered relative to the columns of element contacts (132). Columns (104A, 104B) of package terminals can extend in the first direction. First terminals exposed at a central region (112) of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region (112) may have a width (152) not more than three and one-half times a minimum pitch (150) between the columns of package terminals. The axial plane can intersect the central region.
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