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    CAPACITIVE COUPLING IN A DIRECT-BONDED INTERFACE FOR MICROELECTRONIC DEVICES
    1.
    发明申请
    CAPACITIVE COUPLING IN A DIRECT-BONDED INTERFACE FOR MICROELECTRONIC DEVICES 审中-公开

    公开(公告)号：WO2020117336A1

    公开(公告)日：2020-06-11

    申请号：PCT/US2019/048530

    申请日：2019-08-28

    Applicant: INVENSAS CORPORATION

    Inventor： HABA, Belgacem ,  SITARAM, Arkalgud R.

    IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/311 ,  H01L21/02

    Abstract: Capacitive couplings in a direct- bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct- bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line. The capacitive couplings result from the same direct bonding process that creates the conductive interconnects direct- bonded together at the same bonding interface.

    DEFORMABLE ELECTRICAL CONTACTS WITH CONFORMABLE TARGET PADS
    2.
    发明申请
    DEFORMABLE ELECTRICAL CONTACTS WITH CONFORMABLE TARGET PADS 审中-公开

    公开(公告)号：WO2018231442A1

    公开(公告)日：2018-12-20

    申请号：PCT/US2018/033833

    申请日：2018-05-22

    Applicant: INVENSAS CORPORATION

    Inventor： HABA, Belgacem ,  GUEVARA, Gabriel Z.

    IPC: H01L23/498

    Abstract: Deformable electrical contacts with conformable target pads for microelectronic assemblies and other applications are provided. A plurality of deformable electrical contacts on a first substrate may be joined to a plurality of conformable pads on a second substrate during die level or wafer level assembly of microelectronics, for example. Each deformable contact deforms to a degree that is related to the amount of joining pressure between the first substrate and the second substrate. The deformation process also wipes each respective conformable pad with the deformable electrical contact to create a fresh metal-to-metal contact for good conduction. Each conformable pad collapses as pressured by a compressible material to assume the approximate deformed shape of the electrical contact, providing a large conduction surface area, while also compensating for horizontal misalignment. Temperature can be raised to melt a dielectric, which encapsulates the electrical connections, equalizes gaps and variations between the two substrates, and permanently secures the two substrates together.

    WARPAGE BALANCING IN THIN PACKAGES
    3.
    发明申请
    WARPAGE BALANCING IN THIN PACKAGES 审中-公开
    在薄包装中的翘曲平衡

    公开(公告)号：WO2018031457A1

    公开(公告)日：2018-02-15

    申请号：PCT/US2017/045711

    申请日：2017-08-07

    Applicant: INVENSAS CORPORATION

    Inventor： HABA, Belgacem ,  LEE, Sangil ,  MITCHELL, Craig ,  GUEVARA, Gabriel, Z. ,  DELACRUZ, Javier, A.

    IPC: H01L23/498 ,  H01L25/07 ,  H01L23/00

    Abstract: Representative implementations of devices and techniques provide reinforcement for a carrier or a package. A reinforcement layer is added to a surface of the carrier, often a bottom surface of the carrier that is generally under-utilized except for placement of terminal connections. The reinforcement layer adds structural support to the carrier or package, which can be very thin otherwise. In various embodiments, the addition of the reinforcement layer to the carrier or package reduces warpage of the carrier or package.

    Abstract translation: 器件和技术的代表性实现为载体或封装提供了强化。 增强层被添加到载体的表面，通常是除了放置端子连接之外通常未充分利用的载体的底表面。 加强层为载体或包装增加了结构支撑，否则可能非常薄。 在各种实施例中，将增强层添加到载体或包装减少了载体或包装的翘曲。

    NANOSCALE INTERCONNECT ARRAY FOR STACKED DIES
    4.
    发明申请
    NANOSCALE INTERCONNECT ARRAY FOR STACKED DIES 审中-公开
    纳米级互连阵列堆叠模块

    公开(公告)号：WO2017192357A1

    公开(公告)日：2017-11-09

    申请号：PCT/US2017/029881

    申请日：2017-04-27

    Applicant: INVENSAS CORPORATION

    Inventor： WANG, Liang ,  LEE, Bongsub ,  HABA, Belgacem ,  LEE, Sangil

    IPC: H01L21/768

    Abstract: A microelectronic assembly including an insulating layer having a plurality of nanoscale conductors disposed in a nanoscale pitch array therein and a pair of microelectronic elements is provided. The nanoscale conductors can form electrical interconnections between contacts of the microelectronic elements while the insulating layer can mechanically couple the microelectronic elements together.

    Abstract translation: 提供了一种微电子组件，该微电子组件包括具有以纳米级节距阵列布置的多个纳米级导体的绝缘层和一对微电子元件。 纳米级导体可以在微电子元件的触点之间形成电互连，而绝缘层可以将微电子元件机械地耦合在一起。

    METHOD AND STRUCTURES FOR HEAT DISSIPATING INTERPOSERS
    7.
    发明申请
    METHOD AND STRUCTURES FOR HEAT DISSIPATING INTERPOSERS 审中-公开
    热交换器的方法和结构

    公开(公告)号：WO2014100200A1

    公开(公告)日：2014-06-26

    申请号：PCT/US2013/076158

    申请日：2013-12-18

    Applicant: INVENSAS CORPORATION

    Inventor： UZOH, Cyprian Emeka ,  MONADGEMI, Pezhman ,  CASKEY, Terrence ,  AYATOLLAHI, Fatima Lina ,  HABA, Belgacem ,  WOYCHIK, Charles G. ,  NEWMAN, Michael

    IPC: H01L23/48 ,  H01L23/367

    CPC classification number: H01L23/49827 ,  H01L21/76829 ,  H01L21/76898 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2924/00 ,  H01L2924/0002

    Abstract: A method for making an interconnect element includes depositing a thermally conductive layer (38) on an in-process unit (10). The in-process unit includes a semiconductor material layer (12) defining a surface and edges surrounding the surface, a plurality of conductive elements (20), each conductive element having a first portion extending through the semiconductor material layer and a second portion extending from the surface of the semiconductor material layer. Dielectric coatings (28) extend over at least the second portion of each conductive element. The thermally conductive layer (38) is deposited on the in-process unit at a thickness of at least 10 microns so as to overlie a portion of the surface of the semiconductor material layer between the second portions of the conductive elements with the dielectric coatings positioned between the conductive elements and the thermally conductive layer.

    Abstract translation: 制造互连元件的方法包括在工艺处理单元（10）上沉积导热层（38）。 处理单元包括限定表面和围绕表面的边缘的半导体材料层（12），多个导电元件（20），每个导电元件具有延伸穿过半导体材料层的第一部分和从第二部分延伸的第二部分 半导体材料层的表面。 电介质涂层（28）至少在每个导电元件的第二部分上延伸。 导热层（38）以至少10微米的厚度沉积在处理单元上，以覆盖导电元件的第二部分之间的半导体材料层的表面的一部分，其中定位的电介质涂层 在导电元件和导热层之间。

    MICROELECTRONIC ASSEMBLY WITH THERMALLY AND ELECTRICALLY CONDUCTIVE UNDERFILL
    8.
    发明申请
    MICROELECTRONIC ASSEMBLY WITH THERMALLY AND ELECTRICALLY CONDUCTIVE UNDERFILL 审中-公开

    公开(公告)号：WO2014074933A3

    公开(公告)日：2014-05-15

    申请号：PCT/US2013/069319

    申请日：2013-11-08

    Applicant: INVENSAS CORPORATION

    Inventor： HABA, Belgacem ,  MCELREA, Simon

    IPC: H01L23/552 ,  H01L23/373 ,  H01L23/29 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/60 ,  H01L23/485

    Abstract: A microelectronic assembly may include a microelectronic element having a surface and a plurality of contacts at the surface; a first element consisting essentially of at least one of semiconductor or dielectric material, the first element having a surface facing the surface of the microelectronic element and a plurality of first element contacts at the surface of the first element; electrically conductive masses each joining a contact of the plurality of contacts of the microelectronic element with a respective first element contact of the plurality of first element contacts; a thermally and electrically conductive material layer between the surface of the microelectronic element and the surface of the first element and adjacent conductive masses of the conductive masses; and an electrically insulating coating electrically insulating the conductive masses and the surfaces of the microelectronic element and the first element from the thermally and electrically conductive material layer.

    REDUCED STRESS TSV AND INTERPOSER STRUCTURES
    9.
    发明申请
    REDUCED STRESS TSV AND INTERPOSER STRUCTURES 审中-公开

    公开(公告)号：WO2013184921A3

    公开(公告)日：2013-12-12

    申请号：PCT/US2013/044519

    申请日：2013-06-06

    Applicant: INVENSAS CORPORATION

    Inventor： UZOH, Cyprian Emeka ,  WOYCHIK, Charles G. ,  CASKEY, Terrence ,  DESAI, Kishor V. ,  WEI, Huailiang ,  MITCHELL, Craig ,  HABA, Belgacem

    IPC: H01L21/768 ,  H01L23/48 ,  H01L23/00

    Abstract: A component 10 can include a substrate 20 and a conductive via 40 extending within an opening 30. The substrate 20 can have first and second opposing surfaces 21, 22. A dielectric material 60 can be exposed at an inner wall 32 of the opening 30. The conductive via 40 can define a relief channel 55 within the opening 30 adjacent the first surface 21. The relief channel 55 can have an edge 56 within a first distance D1 from the inner wall 32 in a direction D2 of a plane P parallel to and within five microns below the first surface 21, the first distance being the lesser of one micron and five percent of a maximum width of the opening 30 in the plane. The edge 56 can extend along the inner wall 32 to span at least five percent of a circumference of the inner wall.

    LOW CTE INTERPOSER
    10.
    发明申请
    LOW CTE INTERPOSER 审中-公开

    公开(公告)号：WO2013066504A1

    公开(公告)日：2013-05-10

    申请号：PCT/US2012/055431

    申请日：2012-09-14

    Applicant: INVENSAS CORPORATION ,  HABA, Belgacem ,  DESAI, Kishor

    Inventor： HABA, Belgacem ,  DESAI, Kishor

    IPC: H01L23/498 ,  H01L21/48

    CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49833 ,  H01L24/17 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/17104 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4911 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/19107 ,  Y10T29/49128 ,  Y10T428/24521 ,  Y10T428/24802 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: An interconnection component (10) includes a first support portion (12) and has a plurality of first conductive vias (22) extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end (26) adjacent a first surface (14) and a second end (24) adjacent a second surface (16). A second support portion (30) has a plurality of second conductive vias (40) extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end (44) adjacent the first surface (34) and a second end (42) adjacent the second surface (32). A redistribution layer (50) is disposed between the second surfaces of the first and second support portions, electrically connecting at least some of the first vias with at least some of the second vias. The first and second support portions can have a CTE of less than 12 ppm/°C.

    Abstract translation: 互连部件（10）包括第一支撑部分（12），并且具有多个第一导电通孔（22），其基本垂直于其表面延伸穿过，使得每个通孔具有邻近第一表面（14）的第一端（26） 和邻近第二表面（16）的第二端（24）。 第二支撑部分（30）具有多个第二导电通孔（40），其基本上垂直于其表面延伸穿过，使得每个通孔具有邻近第一表面（34）的第一端（44）和邻近第二端 第二表面（32）。 再分配层（50）设置在第一和第二支撑部分的第二表面之间，将至少一些第一通孔与至少一些第二通孔电连接。 第一和第二支撑部分可以具有小于12ppm /℃的CTE。

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