公开(公告)号：WO2020117336A1

公开(公告)日：2020-06-11

申请号：PCT/US2019/048530

申请日：2019-08-28

Applicant: INVENSAS CORPORATION

Inventor： HABA, Belgacem ,  SITARAM, Arkalgud R.

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/311 ,  H01L21/02

Abstract: Capacitive couplings in a direct- bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct- bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line. The capacitive couplings result from the same direct bonding process that creates the conductive interconnects direct- bonded together at the same bonding interface.

公开(公告)号：WO2019067579A1

公开(公告)日：2019-04-04

申请号：PCT/US2018/052904

申请日：2018-09-26

Applicant: INVENSAS CORPORATION

Inventor： UZOH, Cyprian, Emeka ,  MIRKARIMI, Laura, Wills

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3065

Abstract: A method for forming an interconnect structure in an element is disclosed. The method can include patterning a cavity in a non-conductive material. The method can include exposing a surface of the cavity in the non-conductive material to a surface nitriding treatment. The method can include depositing a conductive material directly onto the treated surface after the exposing.

公开(公告)号：WO2018231442A1

公开(公告)日：2018-12-20

申请号：PCT/US2018/033833

申请日：2018-05-22

Applicant: INVENSAS CORPORATION

Inventor： HABA, Belgacem ,  GUEVARA, Gabriel Z.

IPC: H01L23/498

Abstract: Deformable electrical contacts with conformable target pads for microelectronic assemblies and other applications are provided. A plurality of deformable electrical contacts on a first substrate may be joined to a plurality of conformable pads on a second substrate during die level or wafer level assembly of microelectronics, for example. Each deformable contact deforms to a degree that is related to the amount of joining pressure between the first substrate and the second substrate. The deformation process also wipes each respective conformable pad with the deformable electrical contact to create a fresh metal-to-metal contact for good conduction. Each conformable pad collapses as pressured by a compressible material to assume the approximate deformed shape of the electrical contact, providing a large conduction surface area, while also compensating for horizontal misalignment. Temperature can be raised to melt a dielectric, which encapsulates the electrical connections, equalizes gaps and variations between the two substrates, and permanently secures the two substrates together.

公开(公告)号：WO2018118394A1

公开(公告)日：2018-06-28

申请号：PCT/US2017/064441

申请日：2017-12-04

Applicant: INVENSAS CORPORATION

Inventor： DELACRUZ, Javier, A. ,  PLANTS, William, C.

IPC: G01R31/28

CPC classification number: G01R31/2856 ,  G01R31/2831 ,  G01R31/2884 ,  G01R31/2894

Abstract: The invention pertains to in-wafer testing of integrated circuits. In particular, it pertains to apparatuses and methods for testing small integrated circuits that have pad sizes and pitches that are too small for using conventional wafer probing technology.

公开(公告)号：WO2018031457A1

公开(公告)日：2018-02-15

申请号：PCT/US2017/045711

申请日：2017-08-07

Applicant: INVENSAS CORPORATION

Inventor： HABA, Belgacem ,  LEE, Sangil ,  MITCHELL, Craig ,  GUEVARA, Gabriel, Z. ,  DELACRUZ, Javier, A.

IPC: H01L23/498 ,  H01L25/07 ,  H01L23/00

Abstract: Representative implementations of devices and techniques provide reinforcement for a carrier or a package. A reinforcement layer is added to a surface of the carrier, often a bottom surface of the carrier that is generally under-utilized except for placement of terminal connections. The reinforcement layer adds structural support to the carrier or package, which can be very thin otherwise. In various embodiments, the addition of the reinforcement layer to the carrier or package reduces warpage of the carrier or package.

Abstract translation: 器件和技术的代表性实现为载体或封装提供了强化。 增强层被添加到载体的表面，通常是除了放置端子连接之外通常未充分利用的载体的底表面。 加强层为载体或包装增加了结构支撑，否则可能非常薄。 在各种实施例中，将增强层添加到载体或包装减少了载体或包装的翘曲。

公开(公告)号：WO2017192357A1

公开(公告)日：2017-11-09

申请号：PCT/US2017/029881

申请日：2017-04-27

Applicant: INVENSAS CORPORATION

Inventor： WANG, Liang ,  LEE, Bongsub ,  HABA, Belgacem ,  LEE, Sangil

IPC: H01L21/768

Abstract: A microelectronic assembly including an insulating layer having a plurality of nanoscale conductors disposed in a nanoscale pitch array therein and a pair of microelectronic elements is provided. The nanoscale conductors can form electrical interconnections between contacts of the microelectronic elements while the insulating layer can mechanically couple the microelectronic elements together.

Abstract translation: 提供了一种微电子组件，该微电子组件包括具有以纳米级节距阵列布置的多个纳米级导体的绝缘层和一对微电子元件。 纳米级导体可以在微电子元件的触点之间形成电互连，而绝缘层可以将微电子元件机械地耦合在一起。

公开(公告)号：WO2017083230A1

公开(公告)日：2017-05-18

申请号：PCT/US2016/060841

申请日：2016-11-07

Applicant: INVENSAS CORPORATION

Inventor： SUN, Zhuowen ,  CHEN, Yong ,  BANG, Kyong-Mo

IPC: G11C11/408 ,  G11C5/06 ,  G11C8/18 ,  G11C11/409 ,  H01L23/02 ,  H01L23/64 ,  H01L25/065 ,  H01L25/18

CPC classification number: G11C11/4087 ,  G11C5/063 ,  G11C8/18 ,  G11C11/409 ,  H01L23/02 ,  H01L23/3128 ,  H01L23/64 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A microelectronic assembly can include an address bus comprising a plurality of signal conductors each passing sequentially through first, second, third, and fourth connection regions, and first and second microelectronic packages. The first microelectronic package can include first and second microelectronic elements, and the second microelectronic package can include third and fourth microelectronic elements. Each microelectronic element can be electrically coupled to the address bus via the respective connection region. An electrical characteristic between the first and second connection regions can be within a same tolerance of the electrical characteristic between the second and third connection regions.

Abstract translation: 微电子组件可以包括地址总线，该地址总线包括顺序地通过第一，第二，第三和第四连接区域以及第一和第二微电子封装的多个信号导体。 第一微电子封装可以包括第一微电子元件和第二微电子元件，并且第二微电子封装可以包括第三微电子元件和第四微电子元件。 每个微电子元件可以经由相应的连接区域电耦合到地址总线。 第一和第二连接区域之间的电特性可以在第二和第三连接区域之间的电特性的相同公差内。

公开(公告)号：WO2016203319A1

公开(公告)日：2016-12-22

申请号：PCT/IB2016/001138

申请日：2016-06-14

Applicant: INVENSAS CORPORATION

Inventor： SHEN, Hong ,  WANG, Liang ,  KATKAR, Rajesh ,  WOYCHIK, Charles, G. ,  GAO, Guilian

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L23/053 ,  H01L23/145 ,  H01L23/147 ,  H01L23/15 ,  H01L23/295 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/16153 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/16315 ,  H01L2924/1632 ,  H01L2924/167 ,  H01L2924/16787 ,  H01L2924/16788 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/01029 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Die (110) are attached to an interposer (420), and the interposer/die assembly is placed into a lid cavity (510). The lid (210) is attached to the top of the assembly, possibly to the encapsulant (474) at the top. The lid's legs (520) surround the cavity and extend down below the top surface of the interposer' s substrate (420S), possibly to the level of the bottom surface of the substrate or lower. The legs (520) may or may not be attached to the interposer/die assembly. In fabrication, the interposer wafer (420SW) has trenches (478) which receive the lid's legs during the lid placement. The interposer wafer is later thinned to remove the interposer wafer portion below the legs and to dice the interposer wafer. The thinning process also exposes, on the bottom, conductive vias (450) passing through the interposer substrate. Other features are also provided.

Abstract translation: 模具（110）附接到插入件（420），并且插入器/模具组件被放置在盖腔（510）中。 盖（210）附接到组件的顶部，可能附接到顶部的密封剂（474）。 盖的腿（520）围绕空腔并且向下延伸到插入器的基板（420S）的顶表面下方，可能到底板的底表面的水平或更低。 腿（520）可以或可以不附接到插入件/模具组件。 在制造中，插入器晶片（420SW）具有在盖放置期间接收盖的腿的沟槽（478）。 中间层晶片稍后变薄以去除腿下方的插入片晶片部分并且切割插入片晶片。 薄化工艺还在底部暴露穿过内插衬底的导电通孔（450）。 还提供其他功能。

公开(公告)号：WO2016137895A1

公开(公告)日：2016-09-01

申请号：PCT/US2016/018960

申请日：2016-02-22

Applicant: INVENSAS CORPORATION

Inventor： UZOH, Cypran, Emeka ,  WOYCHIK, Charles, G. ,  SITARAM, Arkalgud, R. ,  SHEN, Hong ,  SUN, Zhuowen ,  WANG, Liang ,  GAO, Guilian

IPC: H01L21/8234

CPC classification number: H01L23/5223 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114') to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

Abstract translation: 在具有穿过衬底（104）并突出在衬底上方的导电通孔（114）的微电子部件中，导电特征（120E.A，120E.B）设置在衬底周围，导电通孔突起（114' ）以形成电容器，电磁屏蔽件以及可能的其他元件。 还提供了其它特征和实施例。

公开(公告)号：WO2016089831A1

公开(公告)日：2016-06-09

申请号：PCT/US2015/063128

申请日：2015-12-01

Applicant: INVENSAS CORPORATION

Inventor： SHEN, Hong ,  WANG, Liang ,  KATKAR, Rajesh

IPC: H01L25/065 ,  H01L21/98 ,  H01L23/055 ,  H01L23/13 ,  H01L23/498

CPC classification number: H01L25/50 ,  H01L23/13 ,  H01L23/24 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06589 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Stacked dies (110) are encapsulated in an interposer's cavity (304) by multiple encapsulant layers (524) formed of moldable material. Conductive paths (520, 620) connect the dies to the cavity's bottom wall (304B) and, through TSVs passing through the bottom wall, to a conductor below the interposer. The conductive paths can be formed in segments each of which is formed in a through-hole (514) in a respective encapsulant layer. Each segment can be formed by electroplating onto a lower segment; the electroplating current can be provided from below the interposer through the TSVs and earlier formed segments. Other features are also provided.

Abstract translation: 堆叠的管芯（110）通过由可模制材料形成的多个密封层（524）封装在插入件的空腔（304）中。 导电路径（520,620）将模具连接到空腔的底壁（304B），并且通过穿过底壁的TSV连接到插入件下方的导体。 导电路径可以形成为各自形成在各个密封层中的通孔（514）中的段。 每个段可以通过电镀形成在下段上; 电镀电流可以通过TSV和较早形成的片段从插入件的下方提供。 还提供其他功能。