公开(公告)号：WO2015061539A1

公开(公告)日：2015-04-30

申请号：PCT/US2014/061915

申请日：2014-10-23

Applicant: INVENSAS CORPORATION

Inventor： CRISP, Richard, Dewitt ,  HABA, Belgacem ,  ZOHNI, Wael

IPC: H01L23/13 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/12 ,  H01L23/13 ,  H01L23/50 ,  H01L24/06 ,  H01L24/09 ,  H01L2224/023 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/09151 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/01322 ,  H01L2924/14361 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0248 ,  H05K1/112 ,  H05K1/181 ,  H05K3/3415 ,  H05K2201/10159 ,  Y02P70/611 ,  H01L2924/00

Abstract: A microelectronic package has a dielectric element with first and second parallel apertures. A first microelectronic element has contacts overlying the first aperture, and a second microelectronic element has contacts overlying the second aperture. The second microelectronic element can overlie a rear face of the first microelectronic element and the same surface of the dielectric element as the first microelectronic element. First terminals on a second surface of the dielectric element between said first and second apertures can be configured to carry all data signals for read and write access to memory locations within the first and second microelectronic elements.

Abstract translation: 微电子封装具有带有第一和第二平行孔的电介质元件。 第一微电子元件具有覆盖第一孔的触点，并且第二微电子元件具有覆盖第二孔的触点。 第二微电子元件可以覆盖第一微电子元件的后表面和与第一微电子元件相同的介质元件的表面。 位于所述第一和第二孔之间的电介质元件的第二表面上的第一端子可被配置为承载用于对第一和第二微电子元件内的存储器位置的读取和写入访问的所有数据信号。

公开(公告)号：WO2014134118A1

公开(公告)日：2014-09-04

申请号：PCT/US2014/018559

申请日：2014-02-26

Applicant: INVENSAS CORPORATION

Inventor： HABA, Belgacem ,  CRISP, Richard Dewitt ,  ZOHNI, Wael ,  MOHAMMED, Ilyas

IPC: H01L23/12

CPC classification number: H01L23/5386 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/525 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip package has multiple chips (22, 42)that may be arranged side by side or in a staggered, stair step arrangement. The contacts (36, 56) of the chips are connected to interconnect pads (60) carried on the chips themselves or on a redistribution interposer (402). The interconnect pads desirably are arranged in a relatively narrow interconnect zone (62), such that the interconnect pads can be readily wire bonded or otherwise connected to a package substrate.

Abstract translation: 芯片封装具有多个芯片（22,42），其可以并排布置或以交错的阶梯布置布置。 芯片的触点（36,56）连接到芯片本身或再分配插入器（402）上承载的互连焊盘（60）。 互连焊盘理想地布置在相对窄的互连区（62）中，使得互连焊盘可以容易地引线接合或以其他方式连接到封装衬底。

公开(公告)号：WO2013052345A1

公开(公告)日：2013-04-11

申请号：PCT/US2012/057554

申请日：2012-09-27

Applicant: INVENSAS CORPORATION

Inventor： CRISP, Richard, Dewitt ,  ZOHNI, Wael ,  HABA, Belgacem ,  LAMBRECHT, Frank

IPC: H01L23/498 ,  H01L25/065

CPC classification number: G11C5/063 ,  G11C5/04 ,  H01L22/32 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/06179 ,  H01L2224/06181 ,  H01L2224/06515 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73257 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81805 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/1434 ,  H01L2924/1435 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15172 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic package (100) can include a substrate (102) and a microelectronic element (130) having a face (134) and one or more columns (138, 139) of contacts (132) exposed thereat which face and are joined to corresponding contacts exposed at a surface (120) of the substrate. An axial plane (140) may intersect the face along a line in a first direction (142) and centered relative to the columns of element contacts (132). Columns (104A, 104B) of package terminals can extend in the first direction. First terminals exposed at a central region (112) of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region (112) may have a width (152) not more than three and one-half times a minimum pitch (150) between the columns of package terminals. The axial plane can intersect the central region.

Abstract translation: 微电子封装（100）可以包括衬底（102）和微电子元件（130），微电子元件（130）具有暴露在其上的面（134）和一个或多个触点（132）的一个或多个柱（138,139） 在衬底的表面（120）处暴露的触点。 轴向平面（140）可以沿着第一方向（142）上的线与面相交并且相对于元件触点（132）的列居中。 封装端子的列（104A，104B）可以在第一方向上延伸。 在第二表面的中心区域（112）处露出的第一端子可被配置为携带可用于确定微电子元件内的可寻址存储器位置的地址信息。 中心区域（112）可以具有不大于封装端子列之间的最小间距（150）的三分之一的宽度（152）。 轴向平面可以与中心区域相交。

公开(公告)号：WO2013052320A1

公开(公告)日：2013-04-11

申请号：PCT/US2012/057170

申请日：2012-09-26

Applicant: INVENSAS CORPORATION

Inventor： CRISP, Richard, Dewitt ,  ZOHNI, Wael ,  HABA, Belgacem ,  LAMBRECHT, Frank

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/0655 ,  G11C5/04 ,  G11C5/063 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24145 ,  H01L2224/48145 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73209 ,  H01L2224/73257 ,  H01L2224/9202 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: A microelectronic package 100 can include a microelectronic element 101 having element contacts 111, a substrate 102 having first and second surfaces 108, 110, and terminals 104 configured for connecting the package with an external component. The microelectronic element 101 can include a plurality of stacked electrically interconnected semiconductor chips 932, 934. The substrate 102 can have contacts 121 facing the element contacts 111 and joined thereto. The terminals can include first terminals 104 arranged at positions within first and second sets 114, 124 thereof disposed on respective opposite sides of a theoretical axis 132. Each set of first terminals 104 can be configured to carry address information usable by circuitry within the package 100 to determine an addressable memory location in the memory storage array. The signal assignments of the first terminals 104 in the first set 114 can be a mirror image of the signal assignments of the first terminals in the second set 124.

Abstract translation: 微电子封装100可以包括具有元件触点111的微电子元件101，具有第一和第二表面108,110的基板102和被配置为将封装与外部元件连接的端子104。 微电子元件101可以包括多个堆叠的电互连的半导体芯片932,934。衬底102可以具有面向元件触点111并且与其连接的触点121。 端子可以包括布置在位于理论轴132的相应相对侧上的第一和第二组114,124内的位置处的第一端子104.每组第一端子104可被配置为携带可由封装100内的电路使用的地址信息 以确定存储器存储阵列中的可寻址存储器位置。 第一组114中的第一端子104的信号分配可以是第二组124中的第一端子的信号分配的镜像。

公开(公告)号：WO2018080790A1

公开(公告)日：2018-05-03

申请号：PCT/US2017/056067

申请日：2017-10-11

Applicant: INVENSAS CORPORATION

Inventor： DELACRUZ, Javier, A. ,  HABA, Belgacem ,  ZOHNI, Wael ,  WANG, Liang ,  AGRAWAL, Akash

IPC: H01L23/498 ,  H01L23/522 ,  H01L23/00 ,  H01L25/07

Abstract: A microelectronic assembly including first and second laminated microelectronic elements is provided. A patterned bonding layer is disposed on a face of each of the first and second laminated microelectronic elements. The patterned bonding layers are mechanically and electrically bonded to form the microelectronic assembly.

Abstract translation: 提供了包括第一和第二层压微电子元件的微电子组件。 图案化的键合层设置在第一和第二层压微电子元件中的每一个的面上。 图案化的键合层机械和电结合以形成微电子组件。

公开(公告)号：WO2015073409A1

公开(公告)日：2015-05-21

申请号：PCT/US2014/064960

申请日：2014-11-11

Applicant: INVENSAS CORPORATION

Inventor： HABA, Belgacem ,  CO, Reynaldo ,  SAGA CIZEK, Rizza Lee ,  ZOHNI, Wael

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L24/85 ,  B23K20/004 ,  B23K20/005 ,  B23K20/007 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/49811 ,  H01L24/43 ,  H01L24/78 ,  H01L2224/04105 ,  H01L2224/056 ,  H01L2224/432 ,  H01L2224/4382 ,  H01L2224/43985 ,  H01L2224/783 ,  H01L2224/78301 ,  H01L2224/7855 ,  H01L2224/78621 ,  H01L2224/78822 ,  H01L2224/85 ,  H01L2224/85345 ,  H01L2224/85399 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/2064 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: An electrically conductive lead (137) is formed using a bonding tool (104). After bonding the wire (115) to a metal surface (112) and extending a length of the wire beyond the bonding tool, the wire is clamped. Movement of the bonding tool imparts a kink (116) to the wire at a location where the wire is fully separated from any metal element other than the bonding tool. A forming element (334), e.g., an edge or a blade skirt provided at an exterior surface of the bonding tool can help kink the wire. Optionally, twisting the wire while tensioning the wire using the bonding tool can cause the wire to break and define an end (138). The lead then extends from the metal surface (112) to the end (138), and may exhibits a sign of the torsional force applied thereto.

Abstract translation: 使用接合工具（104）形成导电引线（137）。 在将金属丝（115）接合到金属表面（112）上并且将一段长度的金属丝延伸超过接合工具之后，电线被夹紧。 接合工具的移动在线材与除了接合工具之外的任何金属元件完全分离的位置处向线材（116）施加扭结（116）。 形成元件（334），例如设置在接合工具的外表面处的边缘或叶片裙部可以帮助扭结线。 可选地，在使用接合工具张紧线材的同时扭绞线可能导致线断裂并限定端部（138）。 然后，引线从金属表面（112）延伸到端部（138），并且可以表现出施加到其上的扭转力的符号。

公开(公告)号：WO2014120883A1

公开(公告)日：2014-08-07

申请号：PCT/US2014/013770

申请日：2014-01-30

Applicant: INVENSAS CORPORATION

Inventor： HABA, Belgacem ,  ZOHNI, Wael

IPC: H01L23/13 ,  H01L25/065

CPC classification number: H01L25/0652 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/3736 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/50 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/07 ,  H01L2224/04042 ,  H01L2224/06156 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2224/50 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic package 10 can include a substrate 20 having first and second opposed surfaces 21, 22 extending in first and second transverse directions H1, H2 and an opening 26 extending between the first and second surfaces and defining first and second distinct parts 27a, 27b each elongated along a common axis 29 extending in the first direction, first and second microelectronic elements 30a, 30b each having a front surface 31 facing the first surface 21 and a column of contacts 35 at the respective front surface, a plurality of terminals 25 exposed at the second surface, and first and second electrical connections 40 aligned with the respective first and second parts of the opening and extending from at least some of the contacts of the respective first and second microelectronic elements to at least some of the terminals. The column of contacts 35 of the first and second microelectronic elements 30a, 30b can be aligned with the respective first and second parts 27a, 27b of the opening 26.

Abstract translation: 微电子封装10可以包括具有在第一和第二横向方向H1，H2上延伸的第一和第二相对表面21,22的衬底20以及在第一和第二表面之间延伸的开口26，并且限定第一和第二不同部分27a，27b 沿着沿第一方向延伸的公共轴线29延伸;第一和第二微电子元件30a，30b，其各自具有面对第一表面21的前表面31和在相应前表面处的接触柱35，多个端子25暴露在 第二表面以及与开口的相应的第一和第二部分对齐并且从相应的第一和第二微电子元件的至少一些触点延伸到至少一些端子的第一和第二电连接40。 第一和第二微电子元件30a，30b的触点列35可以与开口26的相应的第一和第二部分27a，27b对准。

公开(公告)号：WO2014035951A1

公开(公告)日：2014-03-06

申请号：PCT/US2013/056777

申请日：2013-08-27

Applicant: INVENSAS CORPORATION

Inventor： CRISP, Richard, Dewitt ,  HABA, Belgacem ,  ZOHNI, Wael

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/10 ,  G11C5/06

CPC classification number: H01L25/0652 ,  G11C5/063 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/0655 ,  H01L25/105 ,  H01L2924/0002 ,  H05K1/0298 ,  H05K1/111 ,  H05K2201/10159 ,  H01L2924/00

Abstract: A circuit panel 720 can include contacts 760 exposed at a connection site 761 of a major surface 721 thereof and configured to be coupled to terminals 504 of a microelectronic package 500. The connection site 761 can define a peripheral boundary 764 on the major surface 721 surrounding a group of the contacts 760 that is configured to be coupled to a single microelectronic package 500. The group of contacts 760 can include first, second, third, and fourth sets AO, AO', Al ', Al of first contacts 704. Signal assignments of the first and third sets AO, Al ' of first contacts can be symmetric about a theoretical plane 532 normal to the major surface 721 with signal assignments of the respective second and fourth sets AO ', Al of first contacts. Each of the sets AO, AO', Al ', Al of first contacts 704 can be configured to carry identical signals.

Abstract translation: 电路面板720可以包括暴露在其主表面721的连接位置761处并且被配置为耦合到微电子封装500的端子504的触点760.连接部位761可以在主表面721周围限定外围边界764 一组触点760被配置为耦合到单个微电子封装500.触点组760可以包括第一触头704的第一，第二，第三和第四组AO，AO'，A1'，A1。信号 第一触点的第一和第三组AO，A1'的分配可以关于垂直于主表面721的理论平面532对称，其中第一触点的相应的第二和第四组AO'，A1的信号分配。 第一触点704的组AO，AO'，A1'，A1中的每一个可被配置为携带相同的信号。

公开(公告)号：WO2013052544A1

公开(公告)日：2013-04-11

申请号：PCT/US2012/058557

申请日：2012-10-03

Applicant: INVENSAS CORPORATION

Inventor： CRISP, Richard Dewitt ,  ZOHNI, Wael

IPC: H01L23/498 ,  H01L23/482

CPC classification number: H01L25/105 ,  G11C5/04 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/4822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/06156 ,  H01L2224/06164 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/1052 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H05K1/0243 ,  H05K3/3436 ,  H05K2201/10159 ,  H05K2201/10545 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic package (100) includes a microelectronic element (130) having memory storage array function overlying a first surface (108) of a substrate, the microelectronic element having a plurality of contacts (132) aligned with an aperture (112) in the substrate. First terminals (104) which are configured to carry all address signals transferred to the package can be exposed within a first region (140) of a second substrate surface (110), the first region disposed between the aperture (112) and a peripheral edge of the substrate. The first terminals may be configured to carry all command signals, bank address signals and command signals transferred to the package, the command signals being write enable, row address strobe, and column address strobe.

Abstract translation: 微电子封装（100）包括具有覆盖衬底的第一表面（108）的存储器阵列功能的微电子元件（130），所述微电子元件具有与衬底中的孔（112）对准的多个触点（132） 。 配置为承载传送到包装的所有地址信号的第一端子（104）可以暴露在第二衬底表面（110）的第一区域（140）内，第一区域设置在孔（112）和外围边缘 的基底。 第一端子可以被配置为携带传送到封装的所有命令信号，存储体地址信号和命令信号，命令信号是写使能，行地址选通和列地址选通。

公开(公告)号：WO2013052372A2

公开(公告)日：2013-04-11

申请号：PCT/US2012/057905

申请日：2012-09-28

Applicant: INVENSAS CORPORATION

Inventor： CRISP, Richard, Dewitt ,  ZOHNI, Wael ,  HABA, Belgacem ,  LAMBRECHT, Frank

CPC classification number: G06F1/16 ,  G06F1/18 ,  G11C5/04 ,  G11C5/063 ,  G11C5/066 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/06 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/06156 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic package 10 can include a substrate 20 having first and second surfaces 21, 22 and first and second apertures 26a, 26b extending therebetween, first and second microelectronic elements 30a, 30b each having a surface 31 facing the first surface, terminals 25a exposed at the second surface in a central region 23 thereof, and leads 40 electrically connected between contacts 35 exposed at the surface of each microelectronic element and the terminals. The apertures 26a, 26b can have first and second parallel axes 29a, 29b extending in directions of the lengths of the respective apertures. The central region 23 of the second surface 22 can be disposed between the first and second axes 29a, 29b. The terminals 25a can be configured to carry address information usable by circuitry within the microelectronic package 10 to determine an addressable memory location from among all the available addressable memory locations of a memory storage array of at least one of the microelectronic elements 30a, 30b.

Abstract translation: 微电子封装10可以包括具有第一和第二表面21,22的衬底20和在其间延伸的第一和第二孔26a，26b，第一和第二微电子元件30a，30b，每个具有面向第一表面的表面31， 在其中央区域23中的第二表面和电连接在暴露在每个微电子元件的表面处的触点35和端子之间的引线40。 孔26a，26b可以具有在相应孔的长度方向上延伸的第一和第二平行轴线29a，29b。 第二表面22的中心区域23可以设置在第一和第二轴线29a，29b之间。 终端25a可以被配置为承载可由微电子封装10内的电路使用的地址信息，以从微电子元件30a，30b中的至少一个的存储器存储阵列的所有可寻址的存储器单元中确定可寻址的存储器位置。