Invention Application
WO2017213721A1 WITHIN-ARRAY THROUGH-MEMORY-LEVEL VIA STRUCTURES AND METHOD OF MAKING THEREOF
审中-公开
通过结构在阵列中通过存储器级别及其制造方法
- Patent Title: WITHIN-ARRAY THROUGH-MEMORY-LEVEL VIA STRUCTURES AND METHOD OF MAKING THEREOF
- Patent Title (中): 通过结构在阵列中通过存储器级别及其制造方法
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Application No.: PCT/US2017/019132Application Date: 2017-02-23
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Publication No.: WO2017213721A1Publication Date: 2017-12-14
- Inventor: YU, Jixin , LU, Zhenyu , CHU, Alexander , YAMAGUCHI, Kensuke , OGAWA, Hiroyuki , MAO, Daxin , LI, Yan , ALSMEIER, Johann
- Applicant: SANDISK TECHNOLOGIES LLC
- Applicant Address: 6900 North Dallas Parkway Suite 325 Plano, Texas 75024 US
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: 6900 North Dallas Parkway Suite 325 Plano, Texas 75024 US
- Agency: RADOMSKY, Leon et al.
- Priority: US15/176,674 20160608
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/792 ; H01L27/1157 ; H01L27/11573 ; H01L27/11575 ; H01L27/11582
Abstract:
A semiconductor structure includes a memory-level assembly located over a substrate and including at least one alternating stack and memory stack structures vertically extending through the at least one alternating stack. Each of the at least one an alternating stack includes alternating layers of respective insulating layers and respective electrically conductive layers, and each of the electrically conductive layers in the at least one alternating stack includes a respective opening such that a periphery of a respective spacer dielectric portion located in the opening contacts a sidewall of the respective electrically conductive layers. At least one through-memory-level via structure vertically extends through each of the spacer dielectric portions and the insulating layers.
Information query
IPC分类: