中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

172 records (took 0.022 seconds)

    MICROELECTRONIC DEVICES WITH ACTIVE SOURCE/DRAIN CONTACTS IN TRENCH IN SYMMETRICAL DUAL-BLOCK STRUCTURE, AND RELATED SYSTEMS AND METHODS
    3.
    发明申请
    MICROELECTRONIC DEVICES WITH ACTIVE SOURCE/DRAIN CONTACTS IN TRENCH IN SYMMETRICAL DUAL-BLOCK STRUCTURE, AND RELATED SYSTEMS AND METHODS 审中-公开

    公开(公告)号：WO2023288211A1

    公开(公告)日：2023-01-19

    申请号：PCT/US2022/073627

    申请日：2022-07-12

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： XU, Lifang ,  HILL, Richard J. ,  CHARY, Indra V. ,  HEINECK, Lars P.

    IPC: H01L27/11526 ,  H01L27/11573 ,  H01L27/11548 ,  H01L27/11575

    Abstract: Microelectronic devices include a tiered stack having vertically alternating insulative and conductive structures. A first series of stadiums is defined in the tiered stack within a first block of a dual-block structure. A second series of stadiums is defined in the tiered stack within a second block of the dual-block structure. The first and second series of stadiums are substantially symmetrically structured about a trench at a center of the dual-block structure. The trench extends a width of the first and second series of stadiums. The stadiums of the first and second series of stadiums have opposing staircase structures comprising steps at ends of the conductive structures of the tiered stack. Conductive source/drain contact structures are in the stack and extend substantially vertically from a source/drain region at a floor of the trench. Additional microelectronic devices are also disclosed, as are methods of fabrication and electronic systems.

    THREE-DIMENSIONAL MEMORY DEVICES, SYSTEMS, AND METHODS
    4.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICES, SYSTEMS, AND METHODS 审中-公开

    公开(公告)号：WO2023273302A1

    公开(公告)日：2023-01-05

    申请号：PCT/CN2022/071723

    申请日：2022-01-13

    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

    Inventor： LIU, Wei ,  CHEN, Liang ,  WANG, Yanhong ,  XIA, ZhiLiang ,  YANG, Yuancheng

    IPC: H01L27/1157 ,  H01L27/11575 ,  H01L27/11578 ,  H01L25/0652 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573

    Abstract: A three-dimensional 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first semiconductor layer and an array of NAND memory strings. The second semiconductor structure is under a second side of the first semiconductor layer. The second side of the first semiconductor layer is opposite to the first side of the first semiconductor layer. The second semiconductor structure includes a second semiconductor layer, a first peripheral circuit, and a second peripheral circuit. The first peripheral circuit includes a first transistor in contact with a first side of the second semiconductor layer. The second peripheral circuit includes a second transistor in contact with a second side of the second semiconductor layer. The second side of the second semiconductor layer is opposite to the first side of the second semiconductor layer.

    THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME
    5.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME 审中-公开

    公开(公告)号：WO2023272625A1

    公开(公告)日：2023-01-05

    申请号：PCT/CN2021/103764

    申请日：2021-06-30

    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

    Inventor： CHEN, Liang ,  LIU, Wei ,  WANG, Yanhong ,  XIA, Zhiliang ,  ZHOU, Wenxi ,  ZHANG, Kun ,  YANG, Yuancheng ,  HUANG, Shi Qi

    IPC: H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

    Abstract: A three-dimensional (3D) memory device includes a first semiconductor structure (102), a second semiconductor structure (104), a third semiconductor structure (106), a first bonding interface (103) between the first semiconductor structure (102) and the second semiconductor structure (104), and a second bonding interface (105) between the second semiconductor structure (104) and the third semiconductor structure (106). The first semiconductor structure (102) includes an array of NAND memory strings (208) and a first semiconductor layer (1002) in contact with sources of the array of NAND memory strings (208). The second semiconductor structure (104) includes a first peripheral circuit (1716, 1718) of the array of NAND memory strings (208) including a first transistor (1720, 1722), and a second semiconductor layer (1004) in contact with the first transistor (1720, 1722). A third semiconductor structure (106) includes a second peripheral circuit (1704, 1706) of the array of NAND memory strings (208) including a second transistor (1708, 1710), and a third semiconductor layer (1006) in contact with the second transistor (1708, 1710). The first peripheral circuit (1716, 1718) is between the first bonding interface (103) and the second semiconductor layer (1004). The third semiconductor layer (1006) is between the second peripheral circuit (1704, 1706) and the second bonding interface (105).

    THREE-DIMENSIONAL MEMORY DEVICE WITH MULTILEVEL DRAIN-SELECT ELECTRODES AND METHODS FOR FORMING THE SAME
    7.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE WITH MULTILEVEL DRAIN-SELECT ELECTRODES AND METHODS FOR FORMING THE SAME 审中-公开

    公开(公告)号：WO2022231717A1

    公开(公告)日：2022-11-03

    申请号：PCT/US2022/020454

    申请日：2022-03-15

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： TOBIOKA, Akihiro ,  SHIMIZU, Satoshi ,  CUI, Zhixin

    IPC: H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, where the electrically conductive layers include word-line-level electrically conductive layers and drain-select-level electrically conductive layers located above the word-line-level electrically conductive layers, memory opening fill structures vertically extending through the alternating stack, and drain-select-level contact via structures. A first one of the drain-select level contact structures directly contacts at least a first two of the drain-select-level electrically conductive layers that are vertically spaced apart from each other. A second one of the drain-select level contact structures directly contacts at least a second two of the drain-select-level electrically conductive layers that are vertically spaced apart from each other and which are located below the at least the first two of the drain-select-level electrically conductive layers.

    半導体メモリ装置
    9.
    发明申请
    半導体メモリ装置 审中-公开

    公开(公告)号：WO2022168158A1

    公开(公告)日：2022-08-11

    申请号：PCT/JP2021/003725

    申请日：2021-02-02

    Applicant: ユニサンティス　エレクトロニクス　シンガポール　プライベート　リミテッド ,  作井　康司 ,  原田　望

    Inventor： 作井　康司 SAKUI Koji ,  原田　望 HARADA Nozomu

    IPC: G11C16/04 ,  G11C11/401 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L27/11573

    Abstract: プレート線ＰＬと、ワード線ＷＬ０～ＷＬ２と、ソース線ＳＬと、ビット線ＢＬ０～ＢＬ３と、に印加する電圧を制御して、チャネル半導体層の内部に、インパクトイオン化現象、またはゲート誘起ドレインリーク電流により形成した正孔群を保持するデータ書込み動作と、前記プレート線ＰＬと、前記ワード線ＷＬ０～ＷＬ２と、前記ソース線ＳＬと、前記ビット線ＢＬ０～ＢＬ３と、に印加する電圧を制御して、前記正孔群を前記チャネル半導体層の内部から除去するデータ消去動作と、を行う、メモリセルが複数個行列状に配列するブロックがあり、前記ブロック内の選択する第１のワード線が接続する前記メモリセルの記憶データを前記ビット線ＢＬ０～ＢＬ３に読み出す際に、前記第１のワード線を第１の電圧に、前記第１のワード線に隣接する第２のワード線を第２の電圧に印加する、半導体素子を用いたメモリ装置である。

    CONTACT PADS OF THREE-DIMENSIONAL MEMORY DEVICE AND FABRICATION METHOD THEREOF
    10.
    发明申请
    CONTACT PADS OF THREE-DIMENSIONAL MEMORY DEVICE AND FABRICATION METHOD THEREOF 审中-公开

    公开(公告)号：WO2022120631A1

    公开(公告)日：2022-06-16

    申请号：PCT/CN2020/134864

    申请日：2020-12-09

    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD. [CN]/[CN]

    Inventor： WANG, Yongqing ,  HU, Siping

    IPC: H01L27/1157 ,  H01L27/11573

    Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes providing a substrate, forming memory cells over the substrate, depositing a first dielectric layer to cover the memory cells, forming at least one contact pad over the substrate, depositing a second dielectric layer over the at least one contact pad, forming first connecting pads over the second dielectric layer, bonding the first connecting pads with second connecting pads of a peripheral structure, and exposing the at least one contact pad from a back side of the substrate.

Patent Agency Ranking