公开(公告)号：WO2023077290A1

公开(公告)日：2023-05-11

申请号：PCT/CN2021/128337

申请日：2021-11-03

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： WANG, Qiguang ,  PU, Hao ,  LI, Tuo ,  ZHAO, Yingjie

IPC分类号： H01L27/1157

摘要： Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes forming a layer stack, a channel hole, a blocking layer, a charge trap layer, a tunnel insulation layer, and a channel layer. The surface region of the charge trap layer includes a carbon region that contains a certain amount of carbon elements.

公开(公告)号：WO2023033948A1

公开(公告)日：2023-03-09

申请号：PCT/US2022/037724

申请日：2022-07-20

申请人： MICRON TECHNOLOGY, INC.

发明人： HOPKINS, John, D. ,  LI, Haoyu

IPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11575

摘要： A memory array comprising strings of memory cells comprises conductor tier comprising conductor material. Laterally-spaced memory blocks individually comprising a vertical stack comprises alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Conducting material of a lower of the conductive tiers directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The conducting material in the lower conductive tier comprises upper conductively-doped semiconductive material, lower conductively-doped semiconductive material, and intermediate material vertically there-between. Other embodiments, including method, are disclosed.

公开(公告)号：WO2023028851A1

公开(公告)日：2023-03-09

申请号：PCT/CN2021/115738

申请日：2021-08-31

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： ZHANG, Mingkang

IPC分类号： H01L27/1157

摘要： In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure and a second semiconductor bonded with the first semiconductor structure. The first semiconductor structure includes an array of NAND memory strings, a semiconductor layer in contact with source ends of the array of NAND memory strings, an insulating layer in contact with the semiconductor layer, and a contact structure in the insulating layer. The insulating layer electrically insulates the contact structure from the semiconductor layer. The second semiconductor structure includes a transistor.

公开(公告)号：WO2023028751A1

公开(公告)日：2023-03-09

申请号：PCT/CN2021/115315

申请日：2021-08-30

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： WANG, Xiongyu ,  ZHOU, Yi ,  ZHANG, Li ,  WANG, XinSheng ,  LO, Hsing-An ,  ZHANG, GaoSheng ,  XIA, YuPing ,  XIE, Fei

IPC分类号： H01L27/1157 ,  H01L27/11578 ,  H01L27/11524 ,  H01L27/11551

摘要： In a method for fabricating a semiconductor device, a stack of alternating insulating layers and sacrificial layers are formed over a substrate. A staircase having a plurality of steps are formed in the stack, where each of the plurality of steps has a tread and a riser and further includes a respective pair of the insulating layer and the sacrificial layer over the insulating layer of the respective step. A dielectric layer is formed along the treads and risers of the plurality of steps. The dielectric layer is doped with one or a combination of carbon, phosphorous, boron, arsenic, and oxygen. The sacrificial layers are further replaced with a conductive material to form word line layers that are arranged between the insulating layers. A plurality of word line contacts are formed to extend from the word line layers of the plurality of steps, and further extend through the dielectric layer.

公开(公告)号：WO2023028744A1

公开(公告)日：2023-03-09

申请号：PCT/CN2021/115290

申请日：2021-08-30

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： WANG, Yihuan ,  MIAO, Lina

IPC分类号： H01L27/1157 ,  H01L27/11582 ,  H01L27/11575 ,  H01L23/48

摘要： A semiconductor device includes a first die including a first stack of layers in a first region on a backside of the first die and a second stack of layers in a second region on the backside of the first die. The first stack of layers has a smaller number of different layers than the second stack of layers. A contact structure is formed in the first region on the backside of the first die. The contact structure extends through the first stack of layers and is configured to conductively connect a first conductive structure on a face side of the first die with a second conductive structure on the backside of the first die. The face side is opposite to the backside.

公开(公告)号：WO2023023252A1

公开(公告)日：2023-02-23

申请号：PCT/US2022/040759

申请日：2022-08-18

申请人： APPLIED MATERIALS, INC.

发明人： BHUYAN, Bhaskar Jyoti ,  SHEN, Zeqing ,  ROY, Susmit Singha ,  MALLICK, Abhijit Basu

IPC分类号： H01L27/11524 ,  H01L27/1157 ,  H01L27/11551 ,  H01L27/11578 ,  H01L21/02

摘要： Exemplary methods of semiconductor processing may include etching one or more features partially through a stack of layers formed on a substrate. The methods may include halting the etching prior to penetrating fully through the stack of layers formed on the substrate. The methods may include forming a layer of carbon-containing material along the stack of layers on the substrate. The layer of carbon-containing material may include a metal. The methods may include etching the one or more features fully through the stack of layers on the substrate.

公开(公告)号：WO2023273302A1

公开(公告)日：2023-01-05

申请号：PCT/CN2022/071723

申请日：2022-01-13

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： LIU, Wei ,  CHEN, Liang ,  WANG, Yanhong ,  XIA, ZhiLiang ,  YANG, Yuancheng

IPC分类号： H01L27/1157 ,  H01L27/11575 ,  H01L27/11578 ,  H01L25/0652 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573

摘要： A three-dimensional 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first semiconductor layer and an array of NAND memory strings. The second semiconductor structure is under a second side of the first semiconductor layer. The second side of the first semiconductor layer is opposite to the first side of the first semiconductor layer. The second semiconductor structure includes a second semiconductor layer, a first peripheral circuit, and a second peripheral circuit. The first peripheral circuit includes a first transistor in contact with a first side of the second semiconductor layer. The second peripheral circuit includes a second transistor in contact with a second side of the second semiconductor layer. The second side of the second semiconductor layer is opposite to the first side of the second semiconductor layer.

公开(公告)号：WO2023272625A1

公开(公告)日：2023-01-05

申请号：PCT/CN2021/103764

申请日：2021-06-30

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： CHEN, Liang ,  LIU, Wei ,  WANG, Yanhong ,  XIA, Zhiliang ,  ZHOU, Wenxi ,  ZHANG, Kun ,  YANG, Yuancheng ,  HUANG, Shi Qi

IPC分类号： H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

摘要： A three-dimensional (3D) memory device includes a first semiconductor structure (102), a second semiconductor structure (104), a third semiconductor structure (106), a first bonding interface (103) between the first semiconductor structure (102) and the second semiconductor structure (104), and a second bonding interface (105) between the second semiconductor structure (104) and the third semiconductor structure (106). The first semiconductor structure (102) includes an array of NAND memory strings (208) and a first semiconductor layer (1002) in contact with sources of the array of NAND memory strings (208). The second semiconductor structure (104) includes a first peripheral circuit (1716, 1718) of the array of NAND memory strings (208) including a first transistor (1720, 1722), and a second semiconductor layer (1004) in contact with the first transistor (1720, 1722). A third semiconductor structure (106) includes a second peripheral circuit (1704, 1706) of the array of NAND memory strings (208) including a second transistor (1708, 1710), and a third semiconductor layer (1006) in contact with the second transistor (1708, 1710). The first peripheral circuit (1716, 1718) is between the first bonding interface (103) and the second semiconductor layer (1004). The third semiconductor layer (1006) is between the second peripheral circuit (1704, 1706) and the second bonding interface (105).

公开(公告)号：WO2023272623A1

公开(公告)日：2023-01-05

申请号：PCT/CN2021/103762

申请日：2021-06-30

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： ZHANG, Kun ,  YANG, Yuancheng ,  ZHOU, Wenxi ,  LIU, Wei ,  XIA, Zhiliang ,  CHEN, Liang ,  WANG, Yanhong

IPC分类号： H01L27/1157 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11575 ,  H01L27/11578

摘要： In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a first semiconductor layer, an array of NAND memory strings, and a first peripheral circuit of the array of NAND memory strings. Sources of the array of NAND memory strings are in contact with a first side of the first semiconductor layer. The first peripheral circuit includes a first transistor in contact with a second side of the first semiconductor layer opposite to the first side. The second semiconductor structure includes a second semiconductor layer and a second peripheral circuit of the array of NAND memory strings. The second peripheral circuit includes a second transistor in contact with the second semiconductor layer.

公开(公告)号：WO2023272592A1

公开(公告)日：2023-01-05

申请号：PCT/CN2021/103610

申请日：2021-06-30

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： YANG, Yuancheng ,  ZHOU, Wenxi ,  XIA, Zhiliang ,  LIU, Wei

IPC分类号： H01L27/1157 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11575 ,  H01L27/11578

摘要： In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of memory cells and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of memory cells including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of memory cells including a second transistor, and a third semiconductor layer in contact with the second transistor. The second semiconductor layer is between the first bonding interface and the first peripheral circuit. The third semiconductor layer is between the second bonding interface and the second peripheral circuit.