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1.发明申请
公开(公告)号：WO2017142806A1
公开(公告)日：2017-08-24
申请号：PCT/US2017/017403
申请日：2017-02-10
发明人： YU, Jixin , LU, Zhenyu , OGAWA, Hiroyuki , MAO, Daxin , YAMAGUCHI, Kensuke , LEE, Sung Tae , LEE, Yao-sheng , ALSMEIER, Johann
IPC分类号： H01L27/11575 , H01L27/11573 , H01L27/11582 , H01L27/11548 , H01L27/11556
CPC分类号： H01L21/76805 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/26 , H01L21/76877 , H01L23/5226 , H01L23/5283 , H01L27/11524 , H01L27/11529 , H01L27/11548 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： Contacts to peripheral devices extending through multiple tier structures of a three-dimensional memory device can be formed with minimal additional processing steps. First peripheral via cavities through a first tier structure can be formed concurrently with formation of first memory openings. Sacrificial via fill structures can be formed in the first peripheral via cavities concurrently with formation of sacrificial memory opening fill structures that are formed in the first memory openings. Second peripheral via cavities through a second tier structure can be formed concurrently with formation of word line contact via cavities that extend to top surfaces of electrically conductive layers in the first and second tier structures. After removal of the sacrificial via fill structures, the first and second peripheral via cavities can be filled with a conductive material to form peripheral contact via structures concurrently with formation of word line contact via structures.
摘要翻译： 延伸通过三维存储器装置的多层结构的外围设备的触点可以用最小的附加处理步骤来形成。 通过第一层结构的第一外围通孔腔可与形成第一存储器开口同时形成。 牺牲通孔填充结构可以在第一外围通孔腔中形成，同时形成在第一存储器开口中形成的牺牲存储器开口填充结构。 穿过第二层结构的第二外围通孔腔可与形成延伸到第一和第二层结构中的导电层的顶表面的字线接触通孔腔同时形成。 在去除牺牲通孔填充结构之后，可以用导电材料填充第一和第二外围通孔腔体，以与形成字线接触通孔结构同时形成外围接触通孔结构。
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2.发明申请
公开(公告)号：WO2017112014A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/054018
申请日：2016-09-27
发明人： TOYOMA, Fumiaki , MIZUTANI, Yuki , OGAWA, Hiroyuki , FURIHATA, Yoko , YU, Jixin , KAI, James , LIU, Jin , ALSMEIER, Johann
IPC分类号： H01L27/115
CPC分类号： H01L23/5283 , H01L21/76802 , H01L21/76816 , H01L21/76831 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/528 , H01L27/0288 , H01L27/11524 , H01L27/11529 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.
摘要翻译： 三维NAND存储器件包括位于衬底上或上方的字线驱动器器件，位于字线驱动器器件上方的交替的字线和绝缘层叠层，多个存储器叠层结构， 通过交替堆叠，每个存储器堆叠结构包括存储器膜和垂直半导体沟道，以及将第一存储器块中的字线电耦合到字线驱动器器件的贯穿存储器级通孔结构。 通过存储器级的通孔结构延伸穿过位于第一存储器块的阶梯区域和另一存储器块的阶梯区域之间的通过存储器级别的通孔区域。
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3.发明申请
公开(公告)号：WO2022231674A1
公开(公告)日：2022-11-03
申请号：PCT/US2022/013782
申请日：2022-01-26
IPC分类号： H01L21/311 , H01L27/11517
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory opening fill structures including a respective vertical semiconductor channel and a respective memory film, and support pillar structures including a respective dummy vertical semiconductor channel, a respective dummy memory film, and a vertical stack of dielectric spacer fins located at levels of the electrically conductive layers and interposed between the electrically conductive layers and the respective dummy memory film.
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公开(公告)号：WO2021015826A1
公开(公告)日：2021-01-28
申请号：PCT/US2020/023863
申请日：2020-03-20
发明人： KAI, James , ALSMEIER, Johann , YU, Jixin
IPC分类号： H01L27/11582 , H01L27/1157 , H01L27/11573 , H01L23/522
摘要： A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Memory stack structures are formed through the vertically alternating sequence. The vertically alternating sequence is divided into alternating stacks of insulating layers and sacrificial material layers by forming backside trenches therethrough. Each neighboring pair of alternating stacks is laterally spaced apart from each other by a respective backside trench. The sacrificial material layers are replaced with multipart layers. Each multipart layer includes a respective electrically conductive layer that laterally extends continuously between a respective neighboring pair of backside trenches and at least one dielectric material plate that is a remaining portion of a sacrificial material layer, is laterally enclosed by the respective electrically conductive layer, and is laterally spaced from a most proximal one of the backside trenches by a uniform lateral offset distance.
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5.发明申请THROUGH-MEMORY-LEVEL VIA STRUCTURES BETWEEN STAIRCASE REGIONS IN A THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THEREOF 审中-公开三维记忆装置中阶梯区域之间的结构通过内存级别及其制造方法
公开(公告)号：WO2017213720A1
公开(公告)日：2017-12-14
申请号：PCT/US2017/018714
申请日：2017-02-21
发明人： LU, Zhenyu , YU, Jixin , ALSMEIER, Johann , TOYAMA, Fumiaki , MIZUTANI, Yuki , OGAWA, Hiroyuki , GE, Chun , MAO, Daxin , ZHANG, Yanli , CHU, Alexander , LI, Yan
IPC分类号： H01L27/1158 , H01L29/66 , H01L29/792 , H01L27/1157 , H01L27/11575 , H01L27/11573 , H01L27/11582
CPC分类号： H01L27/11582 , H01L21/4846 , H01L21/4853 , H01L21/486 , H01L23/498 , H01L23/49827 , H01L23/49844 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L29/66833 , H01L29/7926
摘要： Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures. An array of memory stack structures is formed through the alternating stack. Trenches are formed through the alternating stack such that a staircase region is located farther away from a threshold lateral distance from the trenches, while neighboring staircase regions are formed within the threshold lateral distance from the trenches. Portions of the spacer dielectric layers proximal to the trenches are replaced with electrically conductive layers, while a remaining portion of the alternating stack is present in the staircase region. At least one through-memory-level via structure can be formed through the remaining portions of the spacer dielectric layers and the insulating layers to provide a vertically conductive path through a memory-level assembly.
摘要翻译： 在其上具有半导体器件的衬底上形成较低级金属互连结构。 在下层金属互连结构上形成半导体材料层和交替堆叠的间隔物电介质层和绝缘层。 通过交替堆叠形成存储器堆栈结构阵列。 通过交替堆叠形成沟槽，使得阶梯区域位于离沟槽的阈值横向距离更远的位置，而相邻的阶梯区域在沟槽的阈值横向距离内形成。 邻近沟槽的间隔物介电层的部分被导电层替换，而交替叠层的剩余部分存在于阶梯区域中。 至少一个贯穿存储器层的通孔结构可以通过间隔物电介质层和绝缘层的剩余部分形成，以提供通过存储器级组件的垂直导电路径。
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6.发明申请WITHIN-ARRAY THROUGH-MEMORY-LEVEL VIA STRUCTURES AND METHOD OF MAKING THEREOF 审中-公开通过结构在阵列中通过存储器级别及其制造方法
公开(公告)号：WO2017213721A1
公开(公告)日：2017-12-14
申请号：PCT/US2017/019132
申请日：2017-02-23
发明人： YU, Jixin , LU, Zhenyu , CHU, Alexander , YAMAGUCHI, Kensuke , OGAWA, Hiroyuki , MAO, Daxin , LI, Yan , ALSMEIER, Johann
IPC分类号： H01L29/66 , H01L29/792 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582
CPC分类号： H01L27/11582 , H01L23/5226 , H01L23/5283 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： A semiconductor structure includes a memory-level assembly located over a substrate and including at least one alternating stack and memory stack structures vertically extending through the at least one alternating stack. Each of the at least one an alternating stack includes alternating layers of respective insulating layers and respective electrically conductive layers, and each of the electrically conductive layers in the at least one alternating stack includes a respective opening such that a periphery of a respective spacer dielectric portion located in the opening contacts a sidewall of the respective electrically conductive layers. At least one through-memory-level via structure vertically extends through each of the spacer dielectric portions and the insulating layers.
摘要翻译： 半导体结构包括位于衬底上的存储器级组件，并包括至少一个交替堆叠和垂直延伸穿过所述至少一个交替堆叠的存储器堆叠结构。 所述至少一个交替堆叠中的每一个包括各自的绝缘层和相应的导电层的交替层，并且所述至少一个交替堆叠中的每个导电层包括相应的开口，使得相应的间隔物电介质部分 位于开口中接触相应导电层的侧壁。 至少一个贯穿存储器层的通孔结构垂直延伸穿过每个间隔物介电部分和绝缘层。
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7.发明申请THREE DIMENSIONAL MEMORY DEVICE CONTAINING DISCRETE SILICON NITRIDE CHARGE STORAGE REGIONS 审中-公开含离散硅氮化物电荷存储区的三维记忆装置
公开(公告)号：WO2017146808A1
公开(公告)日：2017-08-31
申请号：PCT/US2016/067881
申请日：2016-12-20
发明人： YU, Jixin , LU, Zhenyu , MAO, Daxin , ZHANG, Yanli , SEROV, Andrey , GE, Chun , ALSMEIER, Johann
IPC分类号： H01L27/1157 , H01L27/11582
CPC分类号： H01L27/11582 , H01L21/0214 , H01L21/0223 , H01L21/31111 , H01L21/32 , H01L27/1157 , H01L29/7926
摘要： Discrete silicon nitride portions can be formed at each level of electrically conductive layers in an alternating stack of insulating layers and the electrically conductive layers. The discrete silicon nitride portions can be employed as charge trapping material portions, each of which is laterally contacted by a tunneling dielectric portion on the front side, and by a blocking dielectric portion on the back side. The tunneling dielectric portions may be formed as discrete material portions or portions within a tunneling dielectric layer. The blocking dielectric portions may be formed as discrete material portions or portions within a blocking dielectric layer. The discrete silicon nitride portions can be formed by depositing a charge trapping material layer and selectively removing portions of the charge trapping material layer at levels of the insulating layers. Various schemes may be employed to singulate the charge trapping material layer.
摘要翻译： 可以在绝缘层和导电层的交替堆叠中的每个级别的导电层处形成分立的氮化硅部分。 分立的氮化硅部分可以用作电荷俘获材料部分，其每一个由前侧上的隧穿电介质部分以及后侧上的阻挡电介质部分横向接触。 隧穿介电部分可以形成为隧穿介电层内的分立材料部分或部分。 阻挡电介质部分可以形成为阻挡电介质层内的离散材料部分或部分。 可以通过沉积电荷捕捉材料层并且在绝缘层的水平处选择性地去除部分电荷捕捉材料层来形成离散的氮化硅部分。 可以采用各种方案来分割电荷捕捉材料层。
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8.发明申请A THREE DIMENSIONAL MEMORY DEVICE WITH EPITAXIAL SEMICONDUCTOR PEDESTAL FOR PERIPHERAL TRANSISTORS 审中-公开具有外延晶体管外围半导体激光器的三维存储器件
公开(公告)号：WO2017034646A1
公开(公告)日：2017-03-02
申请号：PCT/US2016/036656
申请日：2016-06-09
发明人： LU, Zhenyu , MAO, Daxin , MIYATA, Koji , ARIYOSHI, Junichi , ALSMEIER, Johann , MATAMIS, George , SHI, Wenguang , XU, Jiyin , HU, Xiaolong , LIN, Andrew , YU, Jixin
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L27/11556 , H01L27/11565 , H01L27/11573 , H01L27/11575
摘要： A method of fabricating a memory device is provided. The method includes forming a first alternating stack of insulator layers and spacer material layers over a semiconductor substrate, etching the first alternating stack to expose a single crystalline semiconductor material, forming a first epitaxial semiconductor pedestal on the single crystalline semiconductor material, such that the first epitaxial semiconductor pedestal is in epitaxial alignment with the single crystalline semiconductor material, forming an array of memory stack structures through the first alternating stack, and forming at least one semiconductor device over the first epitaxial semiconductor pedestal.
摘要翻译： 提供一种制造存储器件的方法。 该方法包括在半导体衬底上形成绝缘体层和隔离材料层的第一交替叠层，蚀刻第一交替堆叠以暴露单晶半导体材料，在单晶半导体材料上形成第一外延半导体基座，使得第一 外延半导体基座与单晶半导体材料进行外延对准，通过第一交替叠层形成存储堆栈结构的阵列，并在第一外延半导体基座上形成至少一个半导体器件。
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9.发明申请
公开(公告)号：WO2022125143A1
公开(公告)日：2022-06-16
申请号：PCT/US2021/035847
申请日：2021-06-04
发明人： MATSUNO, Koichi , YU, Jixin , ALSMEIER, Johann
IPC分类号： H01L27/11578 , H01L27/11551 , H01L27/11575 , H01L27/11548 , H01L27/11568 , H01L27/11521
摘要： A three-dimensional memory device includes layer stacks located over a substrate and laterally spaced apart from each other by backside trenches. Each of the layer stacks includes a respective alternating stack of insulating layers and electrically conductive layers. Memory openings vertically extend through a respective one of the alternating stacks and are filled with a respective memory opening fill structure. Each of the memory opening fill structures includes a respective vertical semiconductor channel and a respective vertical stack of memory elements. Each backside trench fill structure includes a respective row of backside trench bridge structures that are more distal from the substrate than a most distal one of the electrically conductive layers is from the substrate. The backside trench bridge structures can provide structural support during a replacement process that forms the electrically conductive layers.
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10.发明申请
公开(公告)号：WO2020197596A1
公开(公告)日：2020-10-01
申请号：PCT/US2019/063597
申请日：2019-11-27
发明人： YU, Jixin , TOYAMA, Fumiaki , HIGASHITANI, Masaaki , ZHANG, Tong , GE, Chun , LI, Xin Yuan , ALSMEIER, Johann , KAWASAKI, Motoki , OKUYAMA, Arata , GU, Xun , KAJIWARA, Kengo
IPC分类号： G11C16/04 , H01L27/06 , H01L27/1157 , H01L27/11582
摘要： Memory dies on a wafer may include multiple memory blocks including bit lines extending along different directions. Each lithographic exposure process may include a first step in which lithographic patterns in first exposure fields are oriented in one direction, and a second step in which lithographic patterns in second exposure fields are oriented in another direction. The different orientations of bit lines and word lines may change local directions of stress to reduce wafer distortion. A three-dimensional memory device includes a pair of alternating stacks of insulating layers and electrically conductive layers and a backside contact assembly located in the backside trench therebetween. The backside contact assembly includes a composite non-metallic core.
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