Invention Application
- Patent Title: TWO TRANSISTOR FINFET-BASED SPLIT GATE NON-VOLATILE FLOATING GATE FLASH MEMORY AND METHOD OF FABRICATION
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Application No.: PCT/US2019/014816Application Date: 2019-01-23
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Publication No.: WO2019182681A3Publication Date: 2019-09-26
- Inventor: JOURBA, Serguei , DECOBERT, Catherine , FENG, Zhou , KIM, Jimho , LIU, Xian , DO, Nhan
- Applicant: SILICON STORAGE TECHNOLOGY, INC.
- Applicant Address: 450 Holger Way San Jose, CA 95134 US
- Assignee: SILICON STORAGE TECHNOLOGY, INC.
- Current Assignee: SILICON STORAGE TECHNOLOGY, INC.
- Current Assignee Address: 450 Holger Way San Jose, CA 95134 US
- Agency: LIMBACH, Alan, A.
- Priority: US15/933,124 20180322
- Main IPC: H01L27/11524
- IPC: H01L27/11524 ; H01L29/423 ; H01L29/78 ; H01L29/788 ; H01L21/28 ; H01L21/66
Abstract:
A non- volatile memory cell formed on a semiconductor substrate having an upper surface with an upwardly extending fin with opposing first and second side surfaces. First and second electrodes are in electrical contact with first and second portions of the fin. A channel region of the fin includes portions of the first and second side surfaces that extend between the first and second portions of the fin. A floating gate extends along the first side surface of a first portion of the channel region, where no portion of the floating gate extends along the second side surface. A word line gate extends along the first and second side surfaces of a second portion of the channel region. A control gate is disposed over the floating gate. An erase gate has a first portion disposed laterally adjacent to the floating gate and a second portion disposed vertically over the floating gate.
Public/Granted literature
- WO2019182681A8 TWO TRANSISTOR FINFET-BASED SPLIT GATE NON-VOLATILE FLOATING GATE FLASH MEMORY AND METHOD OF FABRICATION Public/Granted day:2019-09-26
Information query
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