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    NEURAL NETWORK CLASSIFIER USING ARRAY OF TWO-GATE NON-VOLATILE MEMORY CELLS
    2.
    发明申请
    NEURAL NETWORK CLASSIFIER USING ARRAY OF TWO-GATE NON-VOLATILE MEMORY CELLS 审中-公开

    公开(公告)号：WO2020149886A1

    公开(公告)日：2020-07-23

    申请号：PCT/US2019/048420

    申请日：2019-08-27

    Applicant: SILICON STORAGE TECHNOLOGY, INC.

    Inventor： TRAN, Hieu, Van ,  LEMKE, Steven ,  TIWARI, Vipin ,  DO, Nhan ,  REITEN, Mark

    IPC: G06N3/063

    Abstract: A neural network device having a first plurality of synapses that includes a plurality of memory cells. Each memory cell includes a floating gate over a first portion of a channel region and a first gate over a second portion of the channel region. The memory cells are arranged in rows and columns. A plurality of first lines each electrically connect together the first gates in one of the memory cell rows, a plurality of second lines each electrically connect together the source regions in one of the memory cell rows, and a plurality of third lines each electrically connect together the drain regions in one of the memory cell columns. The first plurality of synapses receives a first plurality of inputs as electrical voltages on the plurality of third lines, and provides a first plurality of outputs as electrical currents on the plurality of second lines.

    SPLIT-GATE FLASH MEMORY ARRAY WITH BYTE ERASE OPERATION
    4.
    发明申请
    SPLIT-GATE FLASH MEMORY ARRAY WITH BYTE ERASE OPERATION 审中-公开

    公开(公告)号：WO2019221867A1

    公开(公告)日：2019-11-21

    申请号：PCT/US2019/027760

    申请日：2019-04-16

    Applicant: SILICON STORAGE TECHNOLOGY, INC.

    Inventor： LIANG, Hsuan ,  YANG, Jeng-Wei ,  WU, Man-Tang ,  DO, Nhan ,  TRAN, Hieu, Van

    IPC: G11C16/16 ,  G11C16/04

    Abstract: A memory device with memory cells in rows and columns, word lines connecting together the control gates for the memory cell rows, bit lines electrically connecting together the drain regions for the memory cell columns, first sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a first plurality of memory cell columns, second sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a second plurality of memory cell columns, first and second source lines, first select transistors each connected between one of first sub source lines and the first source line, second select transistors each connected between one of second sub source lines and the second source line, and select transistor lines each connected to gates of one of the first select transistors and one of the second select transistors.

    NON-VOLATILE SPLIT GATE MEMORY CELLS WITH INTEGRATED HIGH K METAL CONTROL GATES AND METHOD OF MAKING
    7.
    发明申请
    NON-VOLATILE SPLIT GATE MEMORY CELLS WITH INTEGRATED HIGH K METAL CONTROL GATES AND METHOD OF MAKING 审中-公开

    公开(公告)号：WO2019112756A1

    公开(公告)日：2019-06-13

    申请号：PCT/US2018/060181

    申请日：2018-11-09

    Applicant: SILICON STORAGE TECHNOLOGY, INC.

    Inventor： YANG, Jeng-Wei ,  WU, Man-Tang ,  CHEN, Chun-Ming ,  SU, Chien-Sheng ,  DO, Nhan

    IPC: G11C16/04 ,  H01L27/115

    Abstract: A memory device includes a memory cell, a logic device and a high voltage device formed on the same semiconductor substrate. Portions of the upper surface of the substrate under the memory cell and the high voltage device are recessed relative to the upper surface portion of the substrate under the logic device. The memory cell includes a polysilicon floating gate disposed over a first portion of a channel region of the substrate, a polysilicon word line gate disposed over a second portion of the channel region, a polysilicon erase gate disposed over a source region of the substrate, and a metal control gate disposed over the floating gate and insulated from the floating gate by a composite insulation layer that includes a high-K dielectric. The logic device includes a metal gate disposed over the substrate. The high voltage device includes a polysilicon gate disposed over the substrate.

    METHOD OF FORMING LOW HEIGHT SPLIT GATE MEMORY CELLS
    8.
    发明申请
    METHOD OF FORMING LOW HEIGHT SPLIT GATE MEMORY CELLS 审中-公开
    形成低高度分裂门记忆细胞的方法

    公开(公告)号：WO2018031089A1

    公开(公告)日：2018-02-15

    申请号：PCT/US2017/033243

    申请日：2017-05-18

    Applicant: SILICON STORAGE TECHNOLOGY, INC.

    Inventor： SU, Chien-Sheng ,  YANG, Jeng-Wei ,  WU, Man-Tang ,  CHEN, Chun-Ming ,  TRAN, Hieu Van ,  DO, Nhan

    IPC: H01L27/115 ,  H01L21/28 ,  H01L29/41 ,  H01L29/66 ,  H01L29/788

    Abstract: A method of forming a memory device that includes forming a first insulation layer on a semiconductor substrate, forming a conductive material layer on the first insulation layer, forming an insulation block on the conductive material layer, forming an insulation spacer along a side surface of the insulation block and on the conductive material layer, etching the conductive material layer to form a block of the conductive material disposed directly under the insulation block and the insulation spacer, removing the insulation spacer, forming a second insulation layer having a first portion wrapping around an exposed upper edge of the block of the conductive material and a second portion disposed on a first portion of the first insulation layer over the substrate, and forming a conductive block insulated from the block of the conductive material by the second insulation layer and from the substrate by the first and second insulation layers.

    Abstract translation: 一种形成存储器件的方法，该方法包括：在半导体衬底上形成第一绝缘层;在第一绝缘层上形成导电材料层;在导电材料层上形成绝缘块;形成 沿绝缘块的侧表面和导电材料层上的绝缘间隔体，蚀刻导电材料层以形成直接设置在绝缘块和绝缘间隔体下方的导电材料块，去除绝缘间隔体，形成第二绝缘体 其具有第一部分和第二部分，第一部分缠绕在导电材料块的暴露的上边缘上，第二部分设置在第一绝缘层的第一部分上，并形成与导电材料块绝缘的导电块， 第二绝缘层并且通过第一和第二绝缘层从基板上。

    HALL EFFECT ASSISTED ELECTRON CONFINEMENT IN AN INERTIAL ELECTROSTATIC CONFINEMENT FUSION REACTOR
    9.
    发明申请
    HALL EFFECT ASSISTED ELECTRON CONFINEMENT IN AN INERTIAL ELECTROSTATIC CONFINEMENT FUSION REACTOR 审中-公开
    静电放电保护熔融反应器中的霍尔效应辅助电子限制

    公开(公告)号：WO2017040941A1

    公开(公告)日：2017-03-09

    申请号：PCT/US2016/050124

    申请日：2016-09-02

    Applicant: APOLLO FUSION, INC.

    Inventor： LONGMIER, Benjamin

    IPC: G21B1/03 ,  G21B1/00 ,  H05H1/22 ,  H05H1/54 ,  H05H1/04

    CPC classification number: G21B1/05 ,  G21B1/21 ,  G21B1/23 ,  G21Y2002/201 ,  H05H1/02 ,  Y02E30/126

    Abstract: A fusion reactor includes a vacuum chamber, a fuel source for providing fuel to the vacuum chamber, an evacuation pump for evacuating the fuel from the vacuum chamber, a first electrode disposed in the vacuum chamber and at a chamber axis, a second electrode disposed in the vacuum chamber (which includes an aperture through which the chamber axis extends), magnets disposed in the vacuum chamber for producing a magnetic field along the chamber axis, and control electronics. The control electronics control the fuel source and the evacuation pump to provide a low pressure of the fuel in the vacuum chamber, provide a voltage to the first electrode for producing an electron beam along the chamber axis and through the aperture of the second electrode, and provide one or more voltages to the second electrode for compressing the fuel toward the chamber axis to induce nuclear fusion.

    Abstract translation: 聚合反应器包括真空室，用于向真空室提供燃料的燃料源，用于从真空室排出燃料的抽空泵，设置在真空室中并在腔室轴线处的第一电极，设置在真空室中的第二电极 真空室（其包括腔室轴线延伸通过的孔），设置在真空室中的磁体，用于沿腔室轴线产生磁场，以及控制电子器件。 控制电子装置控制燃料源和抽空泵以提供真空室中的燃料的低压力，向第一电极提供电压，以沿腔室轴线和通过第二电极的孔产生电子束;以及 向第二电极提供一个或多个电压，用于将燃料压向腔室轴线以引起核聚变。

    NON-VOLATILE SPLIT GATE MEMORY CELLS WITH INTEGRATED HIGH K METAL GATE LOGIC DEVICE AND METAL-FREE ERASE GATE, AND METHOD OF MAKING SAME
    10.
    发明申请
    NON-VOLATILE SPLIT GATE MEMORY CELLS WITH INTEGRATED HIGH K METAL GATE LOGIC DEVICE AND METAL-FREE ERASE GATE, AND METHOD OF MAKING SAME 审中-公开
    具有集成的高K金属栅逻辑器件和无金属擦除栅的非挥发性分离栅存储器单元及其制造方法

    公开(公告)号：WO2017014866A1

    公开(公告)日：2017-01-26

    申请号：PCT/US2016/037436

    申请日：2016-06-14

    Applicant: SILICON STORAGE TECHNOLOGY, INC.

    Inventor： SU, Chien-sheng ,  YANG, Jeng-Wei ,  ZHOU, Feng

    IPC: H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115

    CPC classification number: H01L27/11531 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/66484 ,  H01L29/66825 ,  H01L29/7881

    Abstract: A method of forming split gate non-volatile memory cells on the same chip as logic and high voltage devices having HKMG logic gates. The method includes forming the source and drain regions, floating gates, control gates, and the poly layer for the erase gates and word line gates in the memory area of the chip. A protective insulation layer is formed over the memory area, and an HKMG layer and poly layer are formed on the chip, removed from the memory area, and patterned in the logic areas of the chip to form the logic gates having varying amounts of underlying insulation.

    Abstract translation: 在具有HKMG逻辑门的逻辑和高电压器件的同一芯片上形成分离栅非易失性存储单元的方法。 该方法包括在芯片的存储器区域中形成用于擦除栅极和字线栅极的源极和漏极区域，浮动栅极，控制栅极和多晶硅层。 在存储区域上形成保护绝缘层，并且在芯片上形成HKMG层和多晶硅层，从存储区域移除，并在芯片的逻辑区域中图案化以形成具有不同量的底层绝缘体的逻辑门 。

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