公开(公告)号：WO2023080915A1

公开(公告)日：2023-05-11

申请号：PCT/US2022/014744

申请日：2022-02-01

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： TRAN, Hieu Van ,  LY, Anh ,  NGUYEN, Kha ,  PHAM, Hien ,  NGUYEN, Duc

IPC: G11C16/30

Abstract: Numerous embodiments of a transceiver for providing high voltages for use during erase or program operations in a non-volatile memory system are disclosed. In one embodiment, a transceiver comprises a PMOS transistor and a native NMOS transistor. In another embodiment, a transceiver comprises a PMOS transistor, an NMOS transistor, and a native NMOS transistor.

公开(公告)号：WO2022256030A1

公开(公告)日：2022-12-08

申请号：PCT/US2021/052234

申请日：2021-09-27

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： MARKOV, Viktor ,  KOTOV, Alexander

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34

Abstract: A memory device and method for a non-volatile memory cell having a gate that includes programming the memory cell to an initial program state corresponding to a target read current and a threshold voltage, including applying a program voltage having a first value to the gate, storing the first value in a memory, reading the memory cell in a first read operation using a read voltage applied to the gate that is less than the target threshold voltage to generate a first read current, and subjecting the memory cell to additional programming in response to determining that the first read current is greater than the target read current. The additional programming includes retrieving the first value from the memory, determining a second value greater than the first value, and programming the selected non-volatile memory cell that includes applying a program voltage having the second value to the gate.

公开(公告)号：WO2022182378A1

公开(公告)日：2022-09-01

申请号：PCT/US2021/033122

申请日：2021-05-19

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： TRAN, Hieu Van ,  LEMKE, Steven ,  DO, Nhan ,  REITEN, Mark

IPC: G06N3/063 ,  G06F17/16

Abstract: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

公开(公告)号：WO2022071982A1

公开(公告)日：2022-04-07

申请号：PCT/US2021/017005

申请日：2021-02-08

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： WANG, Chunming ,  LIU, Xian ,  SONG, Guo Xiang ,  XING, Leo ,  DO, Nhan

IPC: G11C16/04 ,  H01L29/423

Abstract: A memory device, and method of making the same, that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a first channel region in the substrate extending between the first and second regions, a first floating gate disposed over and insulated from a first portion of the first channel region adjacent to the second region, a first coupling gate disposed over and insulated from the first floating gate, a first word line gate disposed over and insulated from a second portion of the first channel region adjacent the first region, and a first erase gate disposed over and insulated from the first word line gate.

公开(公告)号：WO2022060402A1

公开(公告)日：2022-03-24

申请号：PCT/US2021/014244

申请日：2021-01-20

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： WANG, Chunming ,  SONG, Guo Xiang ,  XING, Leo ,  SUN, Jack ,  LIU, Xian ,  DO, Nhan

IPC: H01L27/11546 ,  H01L29/423

Abstract: A method of forming memory cells, HV devices and logic devices on a substrate, including recessing the upper surface of the memory cell and HV device areas of the substrate, forming a polysilicon layer in the memory cell and HV device areas, forming first trenches through the first polysilicon layer and into the silicon substrate in the memory cell and HV device areas, filling the first trenches with insulation material, forming second trenches into the substrate in the logic device area to form upwardly extending fins, removing portions of the polysilicon layer in the memory cell area to form floating gates, forming erase and word line gates in the memory cell area, HV gates in the HV device area, and dummy gates in the logic device area from a second polysilicon layer, and replacing the dummy gates with metal gates that wrap around the fins.

公开(公告)号：WO2021230907A1

公开(公告)日：2021-11-18

申请号：PCT/US2020/060772

申请日：2020-11-16

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： TRAN, Hieu Van ,  VU, Thuan ,  HONG, Stanley ,  TRINH, Stephen ,  TRAN, Han ,  TIWARI, Vipin ,  PHAM, Hien

IPC: G11C11/54 ,  G11C16/04 ,  G11C16/30

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments contain improved mechanisms for pulling source lines down to ground expeditiously. This is useful, for example, to minimize the voltage drop for a read, program, or erase operation.

公开(公告)号：WO2021194552A1

公开(公告)日：2021-09-30

申请号：PCT/US2020/055606

申请日：2020-10-14

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： ZHOU, Feng ,  LIU, Xian ,  LEMKE, Steven ,  TRAN, Hieu Van ,  DO, Nhan

IPC: H01L27/11524 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11529 ,  H01L27/11551 ,  H01L29/42328 ,  H01L29/66795 ,  H01L29/66825

Abstract: Memory cells formed on upwardly extending fins of a semiconductor substrate, each including source and drain regions with a channel region therebetween, a floating gate extending along the channel region and wrapping around the fin, a word line gate extending along the channel region and wrapping around the fin, a control gate over the floating gate, and an erase gate over the source region. The control gates are a continuous conductive strip of material. First and second fins are spaced apart by a first distance. Third and fourth fins are spaced apart by a second distance. The second and third fins are spaced apart by a third distance greater than the first and second distances. The continuous strip includes a portion disposed between the second and third fins, but no portion of the continuous strip is disposed between the first and second fins nor between the third and fourth fins.

公开(公告)号：WO2021076178A1

公开(公告)日：2021-04-22

申请号：PCT/US2020/022450

申请日：2020-03-12

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： LIANG, Hsuan ,  WU, Man Tang ,  YANG, Jeng-Wei ,  CHANG, Lihsin ,  TRAN, Hieu Van ,  DO, Nhan

IPC: G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/04 ,  H01L29/423

Abstract: A memory cell array with memory cells arranged in rows and columns, first sub source lines each connecting together the source regions in one of the rows and in a first plurality of the columns, second sub source lines each connecting together the source regions in one of the rows and in a second plurality of the columns, a first and second erase gate lines each connecting together all of the erase gates in the first and second plurality of the columns respectively, first select transistors each connected between one of first sub source lines and one of a plurality of source lines, second select transistors each connected between one of second sub source lines and one of the source lines, first select transistor line connected to gates of the first select transistors, and a second select transistor line connected to gates of the second select transistors.

公开(公告)号：WO2021045799A1

公开(公告)日：2021-03-11

申请号：PCT/US2020/022191

申请日：2020-03-11

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： MARKOV, Viktor ,  KOTOV, Alexander

IPC: G11C29/06 ,  G11C29/50 ,  G11C11/56 ,  G11C16/04 ,  G11C29/00 ,  G11C29/04

Abstract: A method of improving stability of a memory device having a controller configured to program each of a plurality of non-volatile memory cells within a range of programming states bounded by a minimum program state and a maximum program state. The method includes testing the memory cells to confirm the memory cells are operational, programming each of the memory cells to a mid-program state, and baking the memory device at a high temperature while the memory cells are programmed to the mid-program state. Each memory cell has a first threshold voltage when programmed in the minimum program state, a second threshold voltage when programmed in the maximum program state, and a third threshold voltage when programmed in the mid-program state. The third threshold voltage is substantially at a mid-point between the first and second threshold voltages, and corresponds to a substantially logarithmic mid-point of read currents.

公开(公告)号：WO2020159580A1

公开(公告)日：2020-08-06

申请号：PCT/US2019/048934

申请日：2019-08-29

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： TRAN, Hieu, Van ,  LEMKE, Steven ,  TIWARI, Vipin ,  DO, Nhan ,  REITEN, Mark

IPC: G06N3/063

Abstract: A neural network device with synapses having memory cells each having source and drain regions in a semiconductor substrate with a channel region extending there between, a floating gate over an entirety of the channel region, and a first gate over the floating gate. First lines each electrically connect together the first gates in one of the memory cell rows, second lines each electrically connect together the source regions in one of the memory cell rows, and third lines each electrically connect together the drain regions in one of the memory cell columns. The synapses are configured to receive a first plurality of inputs as electrical voltages on the first lines or on the second lines, and to provide a first plurality of outputs as electrical currents on the third lines.