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    VERFAHREN ZUR ABSICHERUNG VON KONFIGURATIONSDATEN EINES DATENBUS-TRANSCEIVERS, DATENBUS-TRANSCEIVER UND DATENBUSSYSTEM
    2.
    发明公开
    VERFAHREN ZUR ABSICHERUNG VON KONFIGURATIONSDATEN EINES DATENBUS-TRANSCEIVERS, DATENBUS-TRANSCEIVER UND DATENBUSSYSTEM 审中-公开
    用于保护数据总线收发器，数据总线收发器和数据总线系统的配置数据的方法

    公开(公告)号：EP3289726A1

    公开(公告)日：2018-03-07

    申请号：EP15721195.4

    申请日：2015-04-30

    申请人： Continental Teves AG & Co. OHG ,  NXP USA, Inc.

    发明人： BECKMANN, Tobias ,  JANISZEWSKI, Ireneusz ,  CORNELIUS, Claas ,  GACH, Robert ,  MICHEL, Frank

    IPC分类号： H04L12/12 ,  H04L12/40

    摘要： The invention relates to a method for protecting configuration data from a data bus transceiver (1) that can be operated in a subnetwork mode, wherein the configuration data are provided for comparison with data from data bus messages arriving via a data bus (CAN), wherein a reference checksum for the configuration data is generated and stored, this reference checksum is recurrently checked, and in the event of an alteration being identified, a wake-up signal (WUF) and/or a piece of error information (F) is output. During or after writing of the configuration data to configuration register 2 via data bus SPI or directly before the change to the low-power mode of the electronic control unit, checksum unit 3 is used to form a checksum that is stored in reference checksum register 4.1. In the low-power mode of the electronic control unit, the checksum for the configuration is repeatedly recomputed and compared with the checksum stored in reference checksum register 4.1. Checksum unit 3 stores the recomputed checksum value in checksum register 4.2, and comparison unit 5 then performs a comparison between the data stored in reference checksum register 4.1 and the recomputed checksum stored in reference checksum register 4.2. If the recomputed checksum does not match the stored checksum, then comparison unit 5 is used to trigger a wake-up process on the basis of a configuration error KF. The start of a check can be brought about by internal and/or external triggers.

    VERFAHREN UND ELEKTRONISCHE VORRICHTUNG ZUR PULSMODULIERTEN ANSTEUERUNG EINES VERBRAUCHERS
    5.
    发明公开
    VERFAHREN UND ELEKTRONISCHE VORRICHTUNG ZUR PULSMODULIERTEN ANSTEUERUNG EINES VERBRAUCHERS 审中-公开
    一种用于消费者的脉冲调制控制的方法和电子设备

    公开(公告)号：EP3298693A1

    公开(公告)日：2018-03-28

    申请号：EP16723738.7

    申请日：2016-05-18

    申请人： Continental Teves AG & Co. OHG

    发明人： CHEN, Ling ,  HEINZ, Micha ,  MICHEL, Frank

    IPC分类号： H03K7/06 ,  H03K7/08

    摘要： The invention relates to a method for the pulse-modulated actuation of a load in a vehicle. A period duration (T
    PM ) of a frequency (f
    PM ) of the pulse modulation can be divided into a whole number (N) of sections (T
    STEP ), the duration of each of which corresponds to a multiple of a period duration (T
    OSC ) of a clock signal. The method has the following steps: calculating a frequency (f
    PM+1 ,f
    PM ) or a period duration (T
    PM+1 ,T
    PM ) of a period of the pulse modulation on the basis of an underlying frequency modulation and determining the duration of each section (T
    STEP ) of a period duration (T
    PM ) of the pulse modulation using the calculated frequency (f
    PM+1 ,f
    PM ) or period duration (T
    PM+1 ,T
    PM ) of a period of the pulse modulation. The invention further relates to a corresponding electronic device.

    SCHALTUNGSANORDNUNG UND VERFAHREN ZUR ÜBERWACHUNG VON RADDREHZAHLSENSOREN IN EINEM KRAFTFAHRZEUGSTEUERGERÄT
    6.
    发明公开
    SCHALTUNGSANORDNUNG UND VERFAHREN ZUR ÜBERWACHUNG VON RADDREHZAHLSENSOREN IN EINEM KRAFTFAHRZEUGSTEUERGERÄT 有权
    电路装置和方法用于在机动车辆控制装置监视的车轮速度传感器

    公开(公告)号：EP1913404A1

    公开(公告)日：2008-04-23

    申请号：EP06764319.7

    申请日：2006-08-10

    申请人： Continental Teves AG & Co. oHG

    发明人： TRAPP, Rene ,  MICHEL, Frank

    IPC分类号： G01P3/489 ,  B60T8/88

    CPC分类号： G01P3/489 ,  B60T8/885 ,  B60T2270/416

    摘要： Circuit arrangement (2, 3, 4, 5) in an electronic control device which is connected to at least one wheel speed sensor channel (6, 7, 8, 9) which transmits wheel speed information, in particular as a current signal, the circuit arrangement (2, 3,4, 5) having at least one monitoring module (U1, U2, U3, U4) for the at least one wheel speed sensor channel (6, 7, 8, 9), in which this at least one monitoring module (U1, U2, U3, U4) is suitable for monitoring an excess current fault on at least one wheel speed sensor channel (6, 7, 8, 9), in which, when an excess current fault is detected by the at least one monitoring module (U1, U2, U3, U4) the respective wheel speed sensor channel or channels (6, 7, 8, 9) is/are blocked by a blocking circuit (10, 11, 12, 13) of the circuit arrangement (2, 3, 4, 5), and/or in which the circuit arrangement (2, 3, 4, 5) brings about blocking of the respective wheel sensor channel or channels (6, 7, 8, 9) from outside the circuit arrangement (2, 3, 4 5).

    VERFAHREN ZUR STEUERUNG EINES ELEKTRONISCH KOMMUTIERTEN MEHRPHASIGEN GLEICHSTROMMOTORS
    7.
    发明公开
    VERFAHREN ZUR STEUERUNG EINES ELEKTRONISCH KOMMUTIERTEN MEHRPHASIGEN GLEICHSTROMMOTORS 有权

    公开(公告)号：EP2745392A2

    公开(公告)日：2014-06-25

    申请号：EP12743717.6

    申请日：2012-08-01

    申请人： Continental Teves AG&Co. Ohg

    发明人： HEISE, Andreas ,  HARTMANN, Ralf ,  MICHEL, Frank ,  BITSCH, Christian ,  WARMBIER-LEIDIG, Burkhard ,  STAUDER, Peter ,  KAUFMANN, Tom ,  PACHUR, Andreas

    IPC分类号： H02P6/14

    CPC分类号： H02P6/16 ,  H02P6/085 ,  H02P6/153

    摘要： The invention relates to a method for controlling an electronically commutated polyphase DC motor (BLDC motor) (1) with a pole number ≥ 2 and with a winding system (2) having a plurality of winding phases, in particular three winding phases, comprising a rotor, a stator and a position sensor (3) detecting the position of the rotor and a logic circuit (10) for generating the phase voltages of the winding system (2) depending on the electrical phase angle of the rotor. According to the invention, provision is made for the logic circuit (10) to have a storage means (11) with a lookup table, in which the associated drive values depending on the electrical phase angle of the rotor for generating phase voltages (V
    U , V
    V , V
    W ) for the winding system (2) are stored so as to implement commutation with block-shaped, trapezoidal, sinusoidal or sine-based signal forms or with signal forms which are suitable for commutation, a control unit (30) for producing configuration data for the logic circuit (10) is provided, wherein the configuration data determine at least the commutation form and, depending on the determined commutation form, the associated drive values depending on the electrical phase angle of the rotor determined by means of the quadrature sensor (3) are supplied from the storage means (11) to a PWM generator (15) for generating PWM control signals (V
    U , V
    V , V
    W ), with which the phase currents in the winding system (2) can be controlled. In addition, an apparatus for implementing the method according to the invention is provided.

    摘要翻译： 一种用于控制具有转子，定子和角度传感器的无刷直流电动机（BLDC电机）的方法和用于根据转子的相位角产生绕组的相电压的逻辑电路。 逻辑电路访问一个查找表，其中使用块状，梯形，正弦，基于亚信号的信号波形来实现换向。 为了产生绕组的相电压（VU，VV，VW），为转子的电相角保存驱动值。 控制单元产生用于逻辑电路的配置数据，确定换向形式，并且根据形式，驱动值被提供给PWM发生器，用于根据转子的电相角产生控制信号（VU，VV，VW） 角度，哪些PWM控制信号可用于控制绕组中的相电流。

    VERFAHREN UND INTEGRIERTER SCHALTKREIS ZUR ERH HUNG DER ST&O uml;RFESTIGKEIT
    9.
    发明公开
    VERFAHREN UND INTEGRIERTER SCHALTKREIS ZUR ERH HUNG DER ST&O uml;RFESTIGKEIT 审中-公开
    方法与集成电路非洲经委会挂在ST＆O UML;抗干扰

    公开(公告)号：EP1723523A1

    公开(公告)日：2006-11-22

    申请号：EP05716727.2

    申请日：2005-02-17

    申请人： Continental Teves AG & Co. oHG

    发明人： FEY, Wolfgang ,  HEINZ, Micha ,  TRASKOV, Adrian ,  MICHEL, Frank

    IPC分类号： G06F11/07

    CPC分类号： G06F11/0772 ,  G06F11/0724 ,  G06F11/0736 ,  G06F11/0739 ,  G06F11/1645 ,  G06F11/2215

    摘要： The invention relates to a method for increasing the immunity to interference of an integrated switching circuit (16). According to said method, error signals are transmitted between at least one microprocessor chip or multiple microcontroller (1) and at least one additional component (2) in the form of one or more such error signals. A minimum pulse length, which is independent of the clock pulse frequency of the microprocessor or microprocessors, is defined for said transmission. A signal on an error line with a specific pulse length that is in excess of said minimum length is interpreted as an error. The invention also relates to an integrated switching circuit, which is configured in particular to carry out the aforementioned method and comprises at least one microprocessor chip or multiple microcontroller (1) and at least one additional component (2), which contains in particular separate power components and one or more pulse spreading units and/or signal delay units for the sequential emission of error pulses (6, 6') via at least one error line (3, 4)