公开(公告)号：EP2173034A3

公开(公告)日：2010-05-12

申请号：EP09180525.9

申请日：2005-07-25

申请人： Easic Corporation ,  Kapel, Alon ,  Grigore, George Catalin

发明人： Kapel, Alon ,  Grigore, George Catalin ,  Or-Bach, Zvi ,  Avram, Petrica ,  Iacobut, Romeo ,  Apostol, Adrian ,  Wurman, Ze'ev ,  Leventhal, Adam ,  Zeman, Richard

IPC分类号： H03K19/173

CPC分类号： H03K19/1776 ,  G01R31/3172 ,  G01R31/318516 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2924/14 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17796 ,  H01L2924/00

摘要： A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlaying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

公开(公告)号：EP2173034A2

公开(公告)日：2010-04-07

申请号：EP09180525.9

申请日：2005-07-25

申请人： Easic Corporation ,  Kapel, Alon ,  Grigore, George Catalin

发明人： Kapel, Alon ,  Grigore, George Catalin ,  Or-Bach, Zvi ,  Avram, Petrica ,  Iacobut, Romeo ,  Apostol, Adrian ,  Wurman, Ze'ev ,  Leventhal, Adam ,  Zeman, Richard

IPC分类号： H03K19/173

CPC分类号： H03K19/1776 ,  G01R31/3172 ,  G01R31/318516 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2924/14 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17796 ,  H01L2924/00

摘要： A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlaying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

摘要翻译： 可配置逻辑阵列可以包括：包含查找表的多个逻辑单元; 可定制的金属和覆盖多个逻辑单元的通孔连接层; 多个设备可定制的I / O单元; 多个配置可定制的RAM块; 具有可定制内容的ROM块; 以及具有可自定义I / O的微处理器，用于配置和测试阵列，其中的定制都在单个通孔层上完成。

公开(公告)号：EP1533904A1

公开(公告)日：2005-05-25

申请号：EP04027138.9

申请日：2000-03-10

申请人： Easic Corporation

发明人： Or-Bach, Zvi ,  Zeman, Richard ,  Wurman, Ze'ev ,  Cooke, Laurance

IPC分类号： H03K19/177

CPC分类号： H03K19/17748 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17764 ,  H03K19/1778 ,  H03K19/17796

摘要： A logic array comprises an array of programmable cells having a multiplicity of inputs and outputs. Customized interconnections provide permanent direct interconnections among at least a plurality of the inputs or outputs. Some of the programmable cells are programmable by means of electrical signals supplied thereto. At least some of the customized interconnections are customized by lithography.

摘要翻译： 逻辑阵列包括具有多个输入和输出的可编程单元阵列。 定制互连在至少多个输入或输出之间提供永久的直接互连。 一些可编程单元可以通过提供给它的电信号来编程。 至少一些定制的互连是通过光刻来定制的。