公开(公告)号：EP2173034A3

公开(公告)日：2010-05-12

申请号：EP09180525.9

申请日：2005-07-25

申请人： Easic Corporation ,  Kapel, Alon ,  Grigore, George Catalin

发明人： Kapel, Alon ,  Grigore, George Catalin ,  Or-Bach, Zvi ,  Avram, Petrica ,  Iacobut, Romeo ,  Apostol, Adrian ,  Wurman, Ze'ev ,  Leventhal, Adam ,  Zeman, Richard

IPC分类号： H03K19/173

CPC分类号： H03K19/1776 ,  G01R31/3172 ,  G01R31/318516 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2924/14 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17796 ,  H01L2924/00

摘要： A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlaying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

公开(公告)号：EP1776762A2

公开(公告)日：2007-04-25

申请号：EP05775248.7

申请日：2005-07-25

申请人： Easic Corporation ,  Kapel, Alon ,  Grigore, George Catalin

发明人： OR-BACH, Zvi ,  AVRAM, Petrica ,  IACOBUT, Romeo ,  APOSTOL, Adrian ,  WURMAN, Ze'ev ,  LEVENTHAL, Adam ,  ZEMAN, Richard

IPC分类号： H03K19/173

CPC分类号： H03K19/1776 ,  H03K19/17728 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17796

摘要： A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlaying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

公开(公告)号：EP1579495A2

公开(公告)日：2005-09-28

申请号：EP03814808.6

申请日：2003-12-16

申请人： Easic Corporation

发明人： OR-BACH, Zvi ,  COOKE, Laurence ,  APOSTOL, Adrian ,  IACOBUT, Romeo

IPC分类号： H01L21/44 ,  H01L23/34 ,  H01L27/10

CPC分类号： H01L28/20 ,  H01L23/3114 ,  H01L24/10 ,  H01L27/11803 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/051 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/05005 ,  H01L2224/05541 ,  H01L2924/00014

摘要： A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os (36) and also including the step of forming redistribution layer (32) for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.

公开(公告)号：EP2173034A2

公开(公告)日：2010-04-07

申请号：EP09180525.9

申请日：2005-07-25

申请人： Easic Corporation ,  Kapel, Alon ,  Grigore, George Catalin

发明人： Kapel, Alon ,  Grigore, George Catalin ,  Or-Bach, Zvi ,  Avram, Petrica ,  Iacobut, Romeo ,  Apostol, Adrian ,  Wurman, Ze'ev ,  Leventhal, Adam ,  Zeman, Richard

IPC分类号： H03K19/173

CPC分类号： H03K19/1776 ,  G01R31/3172 ,  G01R31/318516 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2924/14 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17796 ,  H01L2924/00

摘要： A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlaying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

摘要翻译： 可配置逻辑阵列可以包括：包含查找表的多个逻辑单元; 可定制的金属和覆盖多个逻辑单元的通孔连接层; 多个设备可定制的I / O单元; 多个配置可定制的RAM块; 具有可定制内容的ROM块; 以及具有可自定义I / O的微处理器，用于配置和测试阵列，其中的定制都在单个通孔层上完成。

公开(公告)号：EP1533904A1

公开(公告)日：2005-05-25

申请号：EP04027138.9

申请日：2000-03-10

申请人： Easic Corporation

发明人： Or-Bach, Zvi ,  Zeman, Richard ,  Wurman, Ze'ev ,  Cooke, Laurance

IPC分类号： H03K19/177

CPC分类号： H03K19/17748 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17764 ,  H03K19/1778 ,  H03K19/17796

摘要： A logic array comprises an array of programmable cells having a multiplicity of inputs and outputs. Customized interconnections provide permanent direct interconnections among at least a plurality of the inputs or outputs. Some of the programmable cells are programmable by means of electrical signals supplied thereto. At least some of the customized interconnections are customized by lithography.

摘要翻译： 逻辑阵列包括具有多个输入和输出的可编程单元阵列。 定制互连在至少多个输入或输出之间提供永久的直接互连。 一些可编程单元可以通过提供给它的电信号来编程。 至少一些定制的互连是通过光刻来定制的。

公开(公告)号：EP1161797A1

公开(公告)日：2001-12-12

申请号：EP00909601.7

申请日：2000-03-10

申请人： Easic Corporation

发明人： OR-BACH, Zvi ,  WURMAN, Ze'ev ,  ZEMAN, Richard ,  COOKE, Laurance

IPC分类号： H03K19/177

CPC分类号： H03K19/17748 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17764 ,  H03K19/1778 ,  H03K19/17796

摘要： This invention discloses a personalizable and programmable integrated circuit device including at least first and second programmable logic cells (46), and at least two electrical conductive paths (28) interconnecting the at least first and second programmable logic cells, at least a portion of which can be removed for personalization of the integrated circuit device, wherein the at least first and second programmable logic cells are programmable by the application of an electrical signal thereto.

公开(公告)号：EP2907161A1

公开(公告)日：2015-08-19

申请号：EP13845263.6

申请日：2013-10-10

申请人： Easic Corporation

发明人： ANDREEV, Alexander ,  GRIBOK, Sergey ,  SCEPANOVIC, Ranko, L. ,  TAN, Phey-Chuin ,  KUNG, Chee-Wei

IPC分类号： H01L25/00

CPC分类号： H01L23/525 ,  H01L23/5226 ,  H01L27/11803 ,  H01L2924/0002 ,  H03K19/17736 ,  H01L2924/00

摘要： A via-configurable logic block architecture for a Structured ASIC has a plurality of MOSFET transistor chains connected to one another through vias. In one embodiment there are three chains and the first transistor chain is a NFET transistor chain, the second transistor chain is a PFET transistor chain, and the third transistor chain is a NFET transistor chain. The first, second and third transistor chains are formed into devices made of transistors that are selected from a voltage threshold group consisting of LVT, SVT and HVT devices, where the first and third transistor chains are formed into devices from a voltage threshold group that is different from one another. In another embodiment transistor drive strength may be varied in the transistor chains of the logic block. In yet another embodiment both voltage threshold and drive strength may be varied together in a symmetrical manner.

公开(公告)号：EP1776762B1

公开(公告)日：2012-02-01

申请号：EP05775248.7

申请日：2005-07-25

申请人： Easic Corporation ,  Kapel, Alon ,  Grigore, George Catalin

发明人： OR-BACH, Zvi ,  AVRAM, Petrica ,  IACOBUT, Romeo ,  APOSTOL, Adrian ,  WURMAN, Ze'ev ,  LEVENTHAL, Adam ,  ZEMAN, Richard ,  KAPEL, Alon ,  GRIGORE, George, Catalin

IPC分类号： H03K19/173

CPC分类号： H03K19/1776 ,  H03K19/17728 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17796

摘要： A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlaying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

公开(公告)号：EP1161797B1

公开(公告)日：2004-12-22

申请号：EP00909601.7

申请日：2000-03-10

申请人： Easic Corporation

发明人： OR-BACH, Zvi ,  WURMAN, Ze'ev ,  ZEMAN, Richard ,  COOKE, Laurance

IPC分类号： H03K19/177

CPC分类号： H03K19/17748 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17764 ,  H03K19/1778 ,  H03K19/17796

摘要： This invention discloses a personalizable and programmable integrated circuit device including at least first and second programmable logic cells (46), and at least two electrical conductive paths (28) interconnecting the at least first and second programmable logic cells, at least a portion of which can be removed for personalization of the integrated circuit device, wherein the at least first and second programmable logic cells are programmable by the application of an electrical signal thereto.