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1.发明公开One-transistor dynamic random-access memory 失效Dynamischer Eintransistor-Speicher mit wahlfreiem Zugriff。
公开(公告)号：EP0154871A2
公开(公告)日：1985-09-18
申请号：EP85101986.9
申请日：1985-02-22
申请人： HITACHI, LTD.
发明人： Yatsuda, Yuji , Sunami, Hideo , Minato, Osamu , Aoki, Masakazu , Takagi, Katsuaki , Horiguchi, Masashi , Tamura, Masao
IPC分类号： H01L27/10
CPC分类号： H01L27/10829
摘要： in a semiconductor memory having memory cells, a groove (17) is formed in a semiconductor substrate (10), and a semiconductor layer (20) is charged into said groove (17) via an insulating film (18) to form a capacitor electrode. The semiconductor layer (20) stretches on the insulating film (11) formed on the semiconductor substrate (10) and comes into contact with the substrate (10) passing through a hole formed in the insulating film (11) thereby to form a base portion of a switching MOS transistor. The source and drain regions (151, 152) of the transistor are formed on said semiconductor layer on the insulating film (11).
摘要翻译： 在具有存储单元的半导体存储器中，在半导体衬底（10）中形成沟槽（17），并且通过绝缘膜（18）将半导体层（20）装入所述沟槽（17）中以形成电容器电极 。 半导体层（20）在形成于半导体基板（10）上的绝缘膜（11）上延伸并与通过形成在绝缘膜（11）上的孔的基板（10）接触，形成基部 的开关MOS晶体管。 晶体管的源极和漏极区域（151,152）形成在绝缘膜（11）上的所述半导体层上。
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公开(公告)号：EP0273396A3
公开(公告)日：1991-11-06
申请号：EP87119154.0
申请日：1987-12-23
申请人： HITACHI, LTD.
发明人： Nakagawa, Norio , Takagi, Katsuaki
CPC分类号： G06F12/1027 , G06F12/1036 , G06F12/1081 , G06F13/285 , G06F13/30
摘要： A memory management device which is connected in a virtual address space or a physical address space together with another device capable of becoming a bus master, is endowed with the function of detecting the bus request signal of the other device, interrupting an address translation process under execution and causing a processor to release a bus. Thus, the other device can be made the bus master without being kept waiting for a long time, and a system bug can be prevented which is attributed to such a fact that a wait time exceeds the data hold time of an input/output device connected to, for example, a direct memory access controller.
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公开(公告)号：EP0273396A2
公开(公告)日：1988-07-06
申请号：EP87119154.0
申请日：1987-12-23
申请人： HITACHI, LTD.
发明人： Nakagawa, Norio , Takagi, Katsuaki
CPC分类号： G06F12/1027 , G06F12/1036 , G06F12/1081 , G06F13/285 , G06F13/30
摘要： A memory management device which is connected in a virtual address space or a physical address space together with another device capable of becoming a bus master, is endowed with the function of detecting the bus request signal of the other device, interrupting an address translation process under execution and causing a processor to release a bus. Thus, the other device can be made the bus master without being kept waiting for a long time, and a system bug can be prevented which is attributed to such a fact that a wait time exceeds the data hold time of an input/output device connected to, for example, a direct memory access controller.
摘要翻译： 连接在虚拟地址空间或物理地址空间中的存储器管理装置与能够成为总线主机的另一个设备一起被赋予检测另一个设备的总线请求信号的功能，中断下面的地址转换处理 执行并导致处理器释放总线。 因此，可以将其他设备制成总线主机而不长时间保持等待，并且可以防止系统错误，这是由于等待时间超过连接的输入/输出设备的数据保持时间 例如，直接存储器存取控制器。
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4.发明公开A pulse width modulation circuit and an analog product forming integration circuit using such modulation circuit 失效脉冲宽度调制器和积分电路，用于与这样的脉冲宽度调制器形成的模拟产品。
公开(公告)号：EP0100103A1
公开(公告)日：1984-02-08
申请号：EP83107412.5
申请日：1983-07-27
IPC分类号： H03K7/08
摘要： A pulse width modulation circuit is capable of cancelling the mean error of pulse width modulation with respect to time due to the offset voltage of a triangular wave signal and to the offset voltage of a comparator, by adding simple circuits (FF3, L1, L2) to an existing pulse width modulation circuit (10, CP3). Such pulse width modulation circuit is used preferably in an integration circuit forming the product of two analog signals.
The offset of the triangular wave signal (VA) is cancelled by inverting either the triangular wave signal with respect to the input signal or the input signal with respect to the triangular wave signal, in every predetermined period. To this end, the circuit eliminates the offset of a comparator (CP3) by inverting the output of the comparator and replacing the input terminals of the comparator if the input signal is not inverted, or connecting the input terminal of the comparator as such if the input signal is inverted.-
5.发明公开Circuit for integrating an analog signal and converting it into a digital signal 失效电路集成的模拟信号并将其转换成数字信号。
公开(公告)号：EP0100102A1
公开(公告)日：1984-02-08
申请号：EP83107411.7
申请日：1983-07-27
IPC分类号： G01R21/06
CPC分类号： G01R21/133 , G01R21/00
摘要： An integrator circuit comprises reset means (RST) by which when it is detected that an integrator output Vp for an input analog signal has coincided with a plus or minus reference value, the integral output is reset to the vicinity of the middle of the plus and minus reference values, in effect, without interrupting the integrating operation; a circuit (OR) which produces a pulse each time the coincidence is detected; and a circuit (FF2) which produces a direction signal indicating whether the coincidence results from the increase or decrease of the integral input. The pulses produced in the state in which the direction signal is indicating the increase are counted up, and the pulses produced in the state in which the direction signal is indicating the decrease are counted down, whereby the precise integral value of the input analog signal can be detected.
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6.发明公开A data processor and a debugging apparatus using it 失效达文教授和Debuggerät，das diesen Prozessor benutzt。
公开(公告)号：EP0591753A2
公开(公告)日：1994-04-13
申请号：EP93115196.3
申请日：1993-09-21
申请人： HITACHI, LTD.
IPC分类号： G06F11/00
CPC分类号： G06F11/3652
摘要： The data processor 1 has a mode in which instructions are executed one module at a time, the module being a subroutine of high-level language, and a break is activated immediately after executing a return instruction at the end of the module. This mode is set in the control register (MSCNT) by an emulator. In this mode, a return address, the address to which the processing returns from the subroutine, is saved in the return address hold register (RAH) by using a return address which is stacked at a time of executing a branch instruction. The return address saved in the return address hold register (RAH) is compared by the comparator circuit 52 with the return address which is popped up from the stack into the instruction pointer (IP) at the execution of the return instruction at the end of the subroutine. When they agree, a break is activated.
摘要翻译： 数据处理器1具有一次一个模块执行指令的模式，该模块是高级语言的子程序，并且在执行模块末尾的返回指令之后立即启动中断。 该模式由仿真器在控制寄存器（MSCNT）中设置。 在该模式中，通过使用在执行分支指令时堆叠的返回地址，返回地址（从子程序返回的处理地址）保存在返回地址保持寄存器（RAH）中。 保存在返回地址保持寄存器（RAH）中的返回地址由比较器电路52与返回地址进行比较，该返回地址在执行返回指令结束时从堆栈弹出到指令指针（IP）中 子程序。 当他们同意时，休息被激活。
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公开(公告)号：EP0250952A2
公开(公告)日：1988-01-07
申请号：EP87108330.9
申请日：1987-06-10
申请人： HITACHI, LTD.
发明人： Takagi, Katsuaki
IPC分类号： G06F12/02
CPC分类号： G06F12/0215
摘要： An address information line (3) of a microprocessor (1) informs a memory management unit (4) of such address information that a current address is identical to an address before one bus-cycle or two bus-cycles or is a new address. Since the address information line (3) has a light load, the address information is transmitted at high speed. In addition, if the current address is identical to the address before one or several bus-cycles, address conversion within the memory management unit (4) can be accelerated in such a way that these addresses are temporarily stored in the memory management unit (4), whereupon the corresponding address is read out.
摘要翻译： 微处理器（1）的地址信息线（3）向存储器管理单元（4）通知这样的地址信息，即当前地址与一个总线周期或两个总线周期之前的地址相同或是新的地址。 由于地址信息线（3）具有轻负载，所以高速地发送地址信息。 此外，如果当前地址与一个或多个总线周期之前的地址相同，则可以加速存储器管理单元（4）内的地址转换，使得这些地址临时存储在存储器管理单元（4）中 ），从而读出对应的地址。
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公开(公告)号：EP0154871A3
公开(公告)日：1986-12-03
申请号：EP85101986
申请日：1985-02-22
申请人： HITACHI, LTD.
发明人： Yatsuda, Yuji , Sunami, Hideo , Minato, Osamu , Aoki, Masakazu , Takagi, Katsuaki , Horiguchi, Masashi , Tamura, Masao
IPC分类号： H01L27/10
CPC分类号： H01L27/10829
摘要： in a semiconductor memory having memory cells, a groove (17) is formed in a semiconductor substrate (10), and a semiconductor layer (20) is charged into said groove (17) via an insulating film (18) to form a capacitor electrode. The semiconductor layer (20) stretches on the insulating film (11) formed on the semiconductor substrate (10) and comes into contact with the substrate (10) passing through a hole formed in the insulating film (11) thereby to form a base portion of a switching MOS transistor. The source and drain regions (151, 152) of the transistor are formed on said semiconductor layer on the insulating film (11).
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9.发明授权Circuit for integrating an analog signal and converting it into a digital signal 失效用于集成模拟信号并将其转换为数字信号的电路
公开(公告)号：EP0100102B1
公开(公告)日：1986-10-08
申请号：EP83107411.7
申请日：1983-07-27
IPC分类号： G01R21/06
CPC分类号： G01R21/133 , G01R21/00
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公开(公告)号：EP0591753A3
公开(公告)日：1994-08-03
申请号：EP93115196.3
申请日：1993-09-21
申请人： HITACHI, LTD.
IPC分类号： G06F11/00
CPC分类号： G06F11/3652
摘要： The data processor 1 has a mode in which instructions are executed one module at a time, the module being a subroutine of high-level language, and a break is activated immediately after executing a return instruction at the end of the module. This mode is set in the control register (MSCNT) by an emulator. In this mode, a return address, the address to which the processing returns from the subroutine, is saved in the return address hold register (RAH) by using a return address which is stacked at a time of executing a branch instruction. The return address saved in the return address hold register (RAH) is compared by the comparator circuit 52 with the return address which is popped up from the stack into the instruction pointer (IP) at the execution of the return instruction at the end of the subroutine. When they agree, a break is activated.
摘要翻译： 数据处理器1具有一次执行一个模块的指令的模式，该模块是高级语言的子程序，并且在模块结束处执行返回指令之后立即激活中断。 该模式由仿真器在控制寄存器（MSCNT）中设置。 在这种模式下，通过使用执行分支指令时堆叠的返回地址，将返回地址（处理从子例程返回到的地址）保存在返回地址保持寄存器（RAH）中。 保存在返回地址保持寄存器（RAH）中的返回地址由比较器电路52与在执行返回指令时从堆栈弹出到指令指针（IP）中的返回地址进行比较 子程序。 当他们同意时，休息被激活。
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