公开(公告)号：EP0111307A3

公开(公告)日：1985-11-06

申请号：EP83112313

申请日：1983-12-07

申请人： HITACHI, LTD.

发明人： Hanamura, Shoji ,  Minato, Osamu ,  Sasaki, Toshio ,  Yamamoto, Syuuichi ,  Masuhara, Toshiaki

IPC分类号： H01L27/10 ,  H01L27/06 ,  H01L21/82 ,  G11C11/40

CPC分类号： H01L28/20 ,  H01L27/0738 ,  H01L27/1112

摘要： A semiconductor integrated circuit includes a p-type well region (22) formed on an n-type semiconductor substrate (21). A hole extends from the surface of said p-type well region (22) to the substrate (21) and an intrinsic or lowly doped semiconductor (27) is buried through an insulating film (26) in said hole. This semiconductor (27) is used as a resistor.

公开(公告)号：EP0066429A3

公开(公告)日：1983-12-14

申请号：EP82302613

申请日：1982-05-21

申请人： Hitachi, Ltd.

发明人： Minato, Osamu ,  Masuhara, Toshiaki ,  Sasaki, Toshio ,  Sasaki, Yukio ,  Kinoshita, Masami ,  Sakai, Yoshio ,  Nagasawa, Kouichi

IPC分类号： G11C05/00

CPC分类号： G11C5/005 ,  G11C11/412 ,  H01L27/092 ,  H01L27/11 ,  H01L27/1112

摘要： A semiconductor memory wherein a semiconductor substrate (1) includes a well (3) of selected depth and of a conductivity type opposite to that of the substrate, a MOS transistor circuit constituting a memory cell formed in the surface region of the well and having information storage nodes the lower part of which is covered with an impurity region (30, 40, 56) of the same conductivity type as the well and being shallower in depth and higher in impurity concentration than the well.

摘要翻译： 一种半导体存储器，其中半导体衬底（1）包括具有选定深度的阱（3）并且导电类型与衬底的导电类型相反，构成存储单元的MOS晶体管电路形成在阱的表面区域并具有信息 存储节点的下部覆盖有与阱相同导电类型的杂质区（30,40,56），并且其深度较浅且杂质浓度高于阱。

公开(公告)号：EP0134432A3

公开(公告)日：1985-10-23

申请号：EP84106779

申请日：1984-06-14

申请人： HITACHI, LTD.

发明人： Minato, Osamu ,  Sasaki, Toshio ,  Masuhara, Toshiaki

IPC分类号： H01L27/02

CPC分类号： H01L27/0266

摘要： This invention relates to a protection device of a semiconductor device. The present invention can prevent the drop of a gate breakdown voltage due to miniaturization of a device without impeding the high speed performance of the circuit attached thereto. The invention improves the voltage, that can be applied to the input terminal (51) of the device, by reducing the surface breakdown voltage of a surface breakdown type MOS transistor (43), which is a principal member of a protection device, and reducing the resistance after the breakdown. This can be accomplished, for example, by increasing the concentration of a region (50) in which the MOS transistor (43) is disposed, by reducing the depth of the region, and so forth.

公开(公告)号：EP0154871A2

公开(公告)日：1985-09-18

申请号：EP85101986.9

申请日：1985-02-22

申请人： HITACHI, LTD.

发明人： Yatsuda, Yuji ,  Sunami, Hideo ,  Minato, Osamu ,  Aoki, Masakazu ,  Takagi, Katsuaki ,  Horiguchi, Masashi ,  Tamura, Masao

IPC分类号： H01L27/10

CPC分类号： H01L27/10829

摘要： in a semiconductor memory having memory cells, a groove (17) is formed in a semiconductor substrate (10), and a semiconductor layer (20) is charged into said groove (17) via an insulating film (18) to form a capacitor electrode. The semiconductor layer (20) stretches on the insulating film (11) formed on the semiconductor substrate (10) and comes into contact with the substrate (10) passing through a hole formed in the insulating film (11) thereby to form a base portion of a switching MOS transistor. The source and drain regions (151, 152) of the transistor are formed on said semiconductor layer on the insulating film (11).

摘要翻译： 在具有存储单元的半导体存储器中，在半导体衬底（10）中形成沟槽（17），并且通过绝缘膜（18）将半导体层（20）装入所述沟槽（17）中以形成电容器电极 。 半导体层（20）在形成于半导体基板（10）上的绝缘膜（11）上延伸并与通过形成在绝缘膜（11）上的孔的基板（10）接触，形成基部 的开关MOS晶体管。 晶体管的源极和漏极区域（151,152）形成在绝缘膜（11）上的所述半导体层上。

公开(公告)号：EP0097326A1

公开(公告)日：1984-01-04

申请号：EP83105880.5

申请日：1983-06-15

申请人： HITACHI, LTD.

发明人： Yamamoto, Syuichi ,  Hashimoto, Norikazu ,  Sasaki, Toshio ,  Masuhara, Toshiaki ,  Minato, Osamu ,  Tamaki, Yoichi ,  Hayashida, Tetsuya

IPC分类号： H01L21/76 ,  H01L27/08

CPC分类号： H01L21/76224 ,  H01L21/76202 ,  H01L27/0921

摘要： To the ends of avoiding an abnormal phenomenon such as latch-up attributed to a parasitic element and of enhancing the density of integration, a groove-like insulator layer (20) extending in the depthwise direction of a semiconductor body (1) is formed at a boundary part between a well region (2) and the semiconductor body (1). Owing to the insulator layer (20), conductive regions which would constitute the parasitic element are separated apart, so that the latch-up phenomenon does not arise. Therefore, the area of the well region (2) can be made small, and the density of integration can be made 1.4 times higher than in prior-art LSI circuits.

摘要翻译： 为了避免归因于寄生元件的闩锁的异常现象和增强集成密度的结束，在半导体本体（1）的深度方向上延伸的槽状绝缘体层（20）形成在 阱区域（2）和半导体本体（1）之间的边界部分。 由于绝缘体层（20），将构成寄生元件的导电区域分开，使得不会产生闭锁现象。 因此，可以使阱区域（2）的面积小，并且集成度可以比现有技术的LSI电路高1.4倍。

公开(公告)号：EP0385516A3

公开(公告)日：1991-03-20

申请号：EP90107554.9

申请日：1984-05-24

申请人： HITACHI, LTD.

发明人： Shimohigashi, Katsuhiro ,  Kubo, Masaharu ,  Miyauchi, Katsuki ,  Masuhara, Toshiaki ,  Minato, Osamu

IPC分类号： G11C5/14 ,  G11C11/407

CPC分类号： G11C11/406 ,  G11C5/141 ,  G11C11/4072 ,  G11C11/4074

摘要： In a memory comprising a memory device (24), a voltage gener­ation circuit (6) converts a power source voltage supplied from an external device and generates a substrate bias volt­age. The external device serves to read from, and write into, said memory device (24) and to supply operation power to said memory device (24). Further provided are a first battery (17c) for supplying said substrate bias voltage to said memory de­vice (24) and a second battery (17a, 17b) for supplying power to said memory device (24), when the operating power is not supplied from said external device.

公开(公告)号：EP0134432A2

公开(公告)日：1985-03-20

申请号：EP84106779.6

申请日：1984-06-14

申请人： HITACHI, LTD.

发明人： Minato, Osamu ,  Sasaki, Toshio ,  Masuhara, Toshiaki

IPC分类号： H01L27/02

CPC分类号： H01L27/0266

摘要： This invention relates to a protection device of a semiconductor device. The present invention can prevent the drop of a gate breakdown voltage due to miniaturization of a device without impeding the high speed performance of the circuit attached thereto. The invention improves the voltage, that can be applied to the input terminal (51) of the device, by reducing the surface breakdown voltage of a surface breakdown type MOS transistor (43), which is a principal member of a protection device, and reducing the resistance after the breakdown. This can be accomplished, for example, by increasing the concentration of a region (50) in which the MOS transistor (43) is disposed, by reducing the depth of the region, and so forth.

公开(公告)号：EP0111307A2

公开(公告)日：1984-06-20

申请号：EP83112313.8

申请日：1983-12-07

申请人： HITACHI, LTD.

发明人： Hanamura, Shoji ,  Minato, Osamu ,  Sasaki, Toshio ,  Yamamoto, Syuuichi ,  Masuhara, Toshiaki

IPC分类号： H01L27/10 ,  H01L27/06 ,  H01L21/82

CPC分类号： H01L28/20 ,  H01L27/0738 ,  H01L27/1112

摘要： A semiconductor integrated circuit includes a p-type well region (22) formed on an n-type semiconductor substrate (21). A hole extends from the surface of said p-type well region (22) to the substrate (21) and an intrinsic or lowly doped semiconductor (27) is buried through an insulating film (26) in said hole. This semiconductor (27) is used as a resistor.

摘要翻译： 半导体集成电路包括形成在n型半导体衬底（21）上的p型阱区（22）。 孔从所述p型阱区（22）的表面延伸到衬底（21），并且本征或低掺杂半导体（27）通过所述孔中的绝缘膜（26）掩埋。 该半导体（27）用作电阻器。

公开(公告)号：EP0385516A2

公开(公告)日：1990-09-05

申请号：EP90107554.9

申请日：1984-05-24

申请人： HITACHI, LTD.

发明人： Shimohigashi, Katsuhiro ,  Kubo, Masaharu ,  Miyauchi, Katsuki ,  Masuhara, Toshiaki ,  Minato, Osamu

IPC分类号： G11C5/14 ,  G11C11/407

CPC分类号： G11C11/406 ,  G11C5/141 ,  G11C11/4072 ,  G11C11/4074

摘要： In a memory comprising a memory device (24), a voltage gener­ation circuit (6) converts a power source voltage supplied from an external device and generates a substrate bias volt­age. The external device serves to read from, and write into, said memory device (24) and to supply operation power to said memory device (24). Further provided are a first battery (17c) for supplying said substrate bias voltage to said memory de­vice (24) and a second battery (17a, 17b) for supplying power to said memory device (24), when the operating power is not supplied from said external device.

摘要翻译： 在包括存储器件（24）的存储器中，电压产生电路（6）转换从外部器件提供的电源电压并产生衬底偏置电压。 外部设备用于从所述存储设备（24）读取和写入，并向所述存储设备（24）提供操作电源。 还提供了用于向所述存储装置（24）提供所述衬底偏置电压的第一电池（17c）和用于向所述存储装置（24）供电的第二电池（17a，17b），当不从 说外部设备。

公开(公告)号：EP0134432B1

公开(公告)日：1989-09-13

申请号：EP84106779.6

申请日：1984-06-14

申请人： HITACHI, LTD.

发明人： Minato, Osamu ,  Sasaki, Toshio ,  Masuhara, Toshiaki

IPC分类号： H01L27/02

CPC分类号： H01L27/0266