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    METHOD TO REDUCE TRENCH CAPACITOR LEAKAGE FOR RANDOM ACCESS MEMORY DEVICE
    1.
    发明公开
    METHOD TO REDUCE TRENCH CAPACITOR LEAKAGE FOR RANDOM ACCESS MEMORY DEVICE 审中-公开
    法降低GRABENKONDENSATORLECKENS用于随机存取存储器设备

    公开(公告)号：EP2215653A1

    公开(公告)日：2010-08-11

    申请号：EP07854536.5

    申请日：2007-10-31

    申请人： Agere Systems, Inc.

    发明人： ROSSI, Nace, M. ,  SINGH, Ranbir ,  YUAN, Xiaojun

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/762

    CPC分类号： H01L27/1087 ,  H01L21/76224 ,  H01L27/10829 ,  H01L27/10861

    摘要： The invention, in one aspect, provides a method of manufacturing a semiconductor device. This method includes forming a trench isolation structure (118) in a dynamic random memory region (DRAM) (110) of a semiconductor substrate (109) and patterning an etch mask over the trench isolation structure (118) to expose a portion of the trench isolation structure (118). A portion of the exposed trench isolation structure (118) is removed to form a gate trench (116) therein, wherein the gate trench (116) includes a first corner formed by the semiconductor substrate and a second corner formed by the trench isolation structure. The etch mask is removed from the DRAM region (110) and the at least the first corner of the gate trench is rounded to form a rounded corner (120). This is followed by the formation of an oxide layer (124) over a sidewall of the gate trench (116), the first rounded corner (120), and the semiconductor substrate (109) adjacent the gate trench (116). The trench (116) is filled with a gate material.

    Method for forming a semiconductor memory device with buried contacts
    2.
    发明公开
    Method for forming a semiconductor memory device with buried contacts 有权
    一种用于在一个半导体存储器件的掩埋触点具有深严重电容器过程

    公开(公告)号：EP1732125A2

    公开(公告)日：2006-12-13

    申请号：EP06011004.6

    申请日：2006-05-29

    申请人： Nanya Technology Corporation

    发明人： Lee, Pei-Ing

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10888 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/66621 ,  H01L29/7834

    摘要： A method for forming a semiconductor memory device with buried contacts. A substrate (100) is provided, wherein the substrate has recessed gates (118) and deep trench capacitor devices (102) therein. Protrusions (120) of the recessed gates and upper portions (104) of the deep trench capacitor devices are revealed. Spacers (124) are formed on sidewalls of the upper portions and the protrusions. Buried portions of conductive material (130) are formed in spaces between the spacers. The substrate, the spacers and the buried portions to form parallel shallow trenches are patterned to form parallel shallow trenches (132) for defining active regions. A layer of dielectric material is formed in the shallow trenches, wherein some of the buried portions serve as buried contacts.

    摘要翻译： 一种用于与掩埋触点形成半导体存储器件的方法。 A底（100）被提供，worin衬底在其中具有凹门（118）和深沟槽电容器装置（102）。 凹入栅极与深沟槽电容器的装置的上部（104）的突起（120）显露。 间隔物（124）形成在所述上部分和所述突出的侧壁。 导电材料（130）的掩埋部分形成在间隔物之间​​的空间。 基板，间隔物和埋入部分，以形成平行的浅沟槽图案化，以形成平行的浅沟槽（132），用于活性限定区域。 电介质材料层形成在浅沟槽，worin一些埋设部16用作掩埋触点。

    Halbleiterspeicher mit streifenförmiger Zellplatte
    6.
    发明公开
    Halbleiterspeicher mit streifenförmiger Zellplatte 审中-公开
    具有带状的电池板的半导体存储器

    公开(公告)号：EP0945903A3

    公开(公告)日：2003-08-06

    申请号：EP99103607.0

    申请日：1999-02-24

    申请人： Infineon Technologies AG

    发明人： Owen, Richard

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10829

    摘要： Bei einer Speicheranordnung mit Speicherzellen, bei der jede Speicherzelle einen Auswahltransistor und einen Grabenkondensator umfaßt, wobei die Speicherelektrode (12) von einem Substratbereich entlang der Grabenwand gebildet wird, und bei der die eine gemeinsame Gegenelektrode mehrerer Speicherzellen bildende Zellplatte (14) im Innern des Grabens gebildet ist, wird die Zellplatte an der Substratoberfläche in Form von Streifen strukturiert. Die Streifen können parallel zur Richtung von Zellreihen laufen oder mit dieser Richtung einen Winkel einschließen. Durch die streifenförmige Anordnung wird die minimale Strukturbreite im Bereich der Zellplatte verdoppelt.

    Shallow trench isolation for DRAM trench capacitor
    9.
    发明公开
    Shallow trench isolation for DRAM trench capacitor 失效
    浅沟槽隔离DRAM电容坟墓

    公开(公告)号：EP0908948A3

    公开(公告)日：2001-10-24

    申请号：EP98110953.1

    申请日：1998-06-16

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： Alsmeier, Johann

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10861 ,  H01L27/10829

    摘要： A random access memory cell having a trench capacitor formed below the surface of the substrate. A shallow trench isolation (455) is provided to isolate the memory cell from other memory cells of a memory array. The shallow trench isolation includes a top surface raised above the substrate wherein the amount that the top surface is raised is sufficient to prevent a divot (490) that is subsequently formed from extending below the substrate surface.