Microcomputer
    3.
    发明公开
    Microcomputer 失效
    Mikrorechner

    公开(公告)号:EP0741358A2

    公开(公告)日:1996-11-06

    申请号:EP96302800.6

    申请日:1996-04-22

    申请人: HITACHI, LTD.

    IPC分类号: G06F15/78

    摘要: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

    摘要翻译: 内置存储器分为以下两种类型:第一存储器5和7以及第二存储器4和6,并且分别由第三总线XAB和XDB以及第二总线YAB和YDB并行访问。 由此,CPU核心2可以同时从内置存储器传送两个数据值到DSP引擎3.此外,第三总线XAB和XDB以及第二总线YAB和YDB也与第一总线IAB和IDB分离成为 外部接口并且CPU核心2可以与对第二存储器4和6以及第一存储器5和7的访问并行地访问外部存储器。