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    Microcomputer
    5.
    发明公开
    Microcomputer 失效
    Mikrorechner

    公开(公告)号：EP0741358A2

    公开(公告)日：1996-11-06

    申请号：EP96302800.6

    申请日：1996-04-22

    申请人： HITACHI, LTD.

    发明人： Ohsuga, Hiroshi ,  Kiuchi, Atsushi ,  Hasegawa, Hironobu ,  Baji, Toru ,  Noguchi, Koki ,  Akao, Yasushi ,  Baba, Shiro

    IPC分类号： G06F15/78

    CPC分类号： G06F9/3893 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/345 ,  G06F9/3552 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3877 ,  G06F15/7817

    摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

    摘要翻译： 内置存储器分为以下两种类型：第一存储器5和7以及第二存储器4和6，并且分别由第三总线XAB和XDB以及第二总线YAB和YDB并行访问。 由此，CPU核心2可以同时从内置存储器传送两个数据值到DSP引擎3.此外，第三总线XAB和XDB以及第二总线YAB和YDB也与第一总线IAB和IDB分离成为 外部接口并且CPU核心2可以与对第二存储器4和6以及第一存储器5和7的访问并行地访问外部存储器。

    A semiconductor integrated circuit
    7.
    发明公开
    A semiconductor integrated circuit 失效
    Eine integrierte Halbleiterschaltung。

    公开(公告)号：EP0676764A2

    公开(公告)日：1995-10-11

    申请号：EP95302121.9

    申请日：1995-03-29

    申请人： HITACHI, LTD.

    发明人： Watanabe, Takao ,  Nakagome, Yoshinobu ,  Ishikura, Kazuo ,  Nakagawa, Tetsuya ,  Kiuchi, Atsushi

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1006 ,  G06F17/10 ,  G06F17/15 ,  G06K9/4642

    摘要： Herein disclosed is a semiconductor integrated circuit capable of executing processing operations using two-dimensional data in a high parallelism and at a high speed.
    The semiconductor integrated circuit comprises: a two-dimensional memory array (MAR); a parallel data transfer circuit (TRC) for transferring the data read out in parallel through data lines, in parallel to a processing circuit group by selecting the word lines of the two-dimensional memory array; and the processing circuit group (PE) for executing processing operations in parallel by using the data transferred from said parallel data transfer circuit. Each of the processing circuits can make access to the plurality of series word lines of said two-dimensional memory array and the data lines through the parallel data transfer circuit, and the data lines of the two-dimensional memory array, to which a plurality of adjoining processing circuits can make access, have an overlapped range.
    Since the data lines of the two-dimensional memory array, to which the adjoining processing circuits can make access, have an overlapped range, the convolution processing operations or the like can be ex ecuted in parallel for the two-dimensional data stored in the two-dimensional memory array.

    摘要翻译： 这里公开的是能够以高并行性和高速执行使用二维数据的处理操作的半导体集成电路。 半导体集成电路包括：二维存储器阵列（MAR）; 并行数据传输电路（TRC），用于通过选择二维存储器阵列的字线，将通过数据线并行读出的数据并行地传送到处理电路组; 以及用于通过使用从所述并行数据传送电路传送的数据并行执行处理操作的处理电路组（PE）。 每个处理电路可以通过并行数据传输电路和二维存储器阵列的数据线访问所述二维存储器阵列的多个串行字线和数据线，多个 相邻的处理电路可以进行访问，具有重叠的范围。 由于相邻的处理电路可以进行访问的二维存储器阵列的数据线具有重叠的范围，所以可以并行地对存储在两个存储器中的二维数据进行卷积处理操作等 维数内存数组。