公开(公告)号：EP4359923A1

公开(公告)日：2024-05-01

申请号：EP21940006.6

申请日：2021-12-24

申请人： Intel Corporation

发明人： ZIMMER, Vincent ,  JAIN, Nilesh ,  POORNACHANDRAN, Rajesh ,  DAVARE, Abhijit ,  BALASUBRAMANIAN, Kaushik ,  LACEWELL, Chaunte ,  PUTTANNAIAH, Karan ,  FANG, Jiahao ,  BANIK, Subrata ,  REGUPATHY, Rajaram ,  THOMAS, Salil Mathachan

IPC分类号： G06F9/445 ,  G06N3/063

CPC分类号： G06N3/063 ,  G06F9/4403 ,  G06N3/0464 ,  G06N3/0455 ,  G06N3/092 ,  G06N3/0985 ,  G06N3/044 ,  G06N5/022

公开(公告)号：EP4020209A1

公开(公告)日：2022-06-29

申请号：EP21217626.7

申请日：2021-12-23

申请人： Intel Corporation

发明人： WANG, Ren ,  GOBRIEL, Sameh ,  PAUL, Somnath ,  WANG, Yipeng ,  AUTEE, Priya ,  LAYEK, Abhirupa ,  NARAYANA, Shaman ,  VERPLANKE, Edwin ,  GANGULI, Mrittika ,  TSAI, Jr-Shian ,  SOROKIN, Anton ,  BANERJEE, Suvadeep ,  DAVARE, Abhijit ,  KIRKPATRICK, Desmond ,  SANKARAN, Rajesh M. ,  TIMBADIYA Jaykant B. ,  KABISTHALAM MUTHUKUMAR, Sriram ,  RANGANATHAN, Narayan

IPC分类号： G06F9/50 ,  G06F15/78

摘要： Examples described herein relate to offload circuitry comprising one or more compute engines that are configurable to perform a workload offloaded from a process executed by a processor based on a descriptor particular to the workload. In some examples, the offload circuitry is configurable to perform the workload, among multiple different workloads. In some examples, the multiple different workloads include one or more of: data transformation (DT) for data format conversion, Locality Sensitive Hashing (LSH) for neural network (NN), similarity search, sparse general matrix-matrix multiplication (SpGEMM) acceleration of hash based sparse matrix multiplication, data encode, data decode, or embedding lookup.

公开(公告)号：EP4134821A1

公开(公告)日：2023-02-15

申请号：EP22181918.8

申请日：2022-06-29

申请人： INTEL Corporation

发明人： NURVITADHI, Eriko ,  DAVARE, Abhijit ,  LACEWELL, Chaunte ,  BHIWANDIWALLA, Anahita ,  JAIN, Nilesh ,  POORNACHANDRAN, Rajesh ,  MUNOZ, Juan Pablo ,  BOUTROS, Andrew ,  AKHAURI, Yash

IPC分类号： G06F9/50 ,  G06N3/04

摘要： Methods, apparatus, systems, and articles of manufacture are disclosed for composable machine learning compute nodes. An example apparatus includes interface circuitry to receive a workload, instructions in the apparatus, and processor circuitry to at least one of execute or instantiate the instructions to generate a first configuration of one or more machine-learning models based on a workload, generate a second configuration of hardware, determine an evaluation parameter based on an execution of the workload, the execution of the workload based on the first configuration and the second configuration, and, in response to the evaluation parameter satisfying a threshold, execute the one or more machine-learning models in the first configuration on the hardware in the second configuration, the one or more machine-learning models and the hardware to execute the workload.