公开(公告)号：EP4017005A1

公开(公告)日：2022-06-22

申请号：EP21198867.0

申请日：2021-09-24

申请人： Intel Corporation

发明人： BOYCE, Jill ,  JAIN, Nilesh ,  GANESH, Brinda ,  LEI, Zhijun ,  HURST, Craig ,  HOLLAND, James ,  POSSOS, Sebastian ,  MOHAN, Sumit ,  NOUIRA, Chekib ,  KOSSENTINI, Faouzi ,  TMAR, Hassene ,  BEN AMARA, Foued

IPC分类号： H04N19/42 ,  H04N19/114 ,  H04N19/127 ,  H04N19/176

摘要： Techniques related to distributing the video encoding processing of an input video across hardware and software systems. Such techniques include evaluating the content of the video and determine whether or the encoding operation is best to be done on the hardware system only, software system only or a hybrid hardware and software system.

公开(公告)号：EP4268077A1

公开(公告)日：2023-11-01

申请号：EP21911773.6

申请日：2021-06-25

申请人： INTEL Corporation

发明人： IYER, Ravishankar ,  TICKOO, Omesh ,  JAIN, Nilesh ,  POORNACHANDRAN, Rajesh ,  CORDOURIER MARURI, Hector ,  CAMACHO PEREZ, Jose Rodrigo ,  ZAMORA ESQUIVEL, Julio ,  LOPEZ MEYER, Paulo ,  SALETORE, Vikram ,  NURVITADHI, Eriko ,  CHUA, Vui Seng ,  LACEWELL, Chaunte ,  BHIWANDIWALLA, Anahita ,  KIM, Sejun ,  MUNOZ, Juan, Pablo ,  AKHAURI, Yash ,  CRUZ VARGAS, Jesus Adan

IPC分类号： G06F9/50 ,  G06F15/78 ,  H04L41/00 ,  H04L65/40

公开(公告)号：EP4155913A1

公开(公告)日：2023-03-29

申请号：EP22192249.5

申请日：2022-08-25

申请人： INTEL Corporation

发明人： ADELMAN, Menachem ,  VALENTINE, Robert ,  BAUM, Dan ,  GRADSTEIN, Amit ,  RUBANOVICH, Simon ,  SHEMY, Regev ,  SPERBER, Zeev ,  HEINECKE, Alexander ,  HUGHES, Christopher ,  GEORGANAS, Evangelos ,  CHARNEY, Mark ,  NARKIS, Arik ,  RAPPOPORT, Rinat ,  ZIV, Barukh ,  POLLAK, Yaroslav ,  JAIN, Nilesh ,  AKHAURI, Yash ,  GANESH, Brinda ,  POORNACHANDRAN, Rajesh ,  BOUDOUKH, Guy

IPC分类号： G06F9/30

摘要： Systems, methods, and apparatuses relating sparsity based FMA. In some examples, an instance of a single FMA instruction has one or more fields for an opcode, one or more fields to identify a source/destination matrix operand, one or more fields to identify a first plurality of source matrix operands, one or more fields to identify a second plurality of matrix operands, wherein the opcode is to indicate that execution circuitry is to select a proper subset of data elements from the first plurality of source matrix operands based on sparsity controls from a first matrix operand of the second plurality of matrix operands and perform a FMA.

公开(公告)号：EP4359923A1

公开(公告)日：2024-05-01

申请号：EP21940006.6

申请日：2021-12-24

申请人： Intel Corporation

发明人： ZIMMER, Vincent ,  JAIN, Nilesh ,  POORNACHANDRAN, Rajesh ,  DAVARE, Abhijit ,  BALASUBRAMANIAN, Kaushik ,  LACEWELL, Chaunte ,  PUTTANNAIAH, Karan ,  FANG, Jiahao ,  BANIK, Subrata ,  REGUPATHY, Rajaram ,  THOMAS, Salil Mathachan

IPC分类号： G06F9/445 ,  G06N3/063

CPC分类号： G06N3/063 ,  G06F9/4403 ,  G06N3/0464 ,  G06N3/0455 ,  G06N3/092 ,  G06N3/0985 ,  G06N3/044 ,  G06N5/022

公开(公告)号：EP3963866A2

公开(公告)日：2022-03-09

申请号：EP20801584.2

申请日：2020-04-29

申请人： INTEL Corporation

发明人： GUIM BERNAT, Francesc ,  ASTILLEROS, Ignacio ,  BALLE, Susanne M. ,  BARTFAI-WALCOTT, Katalin ,  BROWNE, John J. ,  CHEN, Li ,  COOPER, Trevor ,  CUSTODIO, Evan ,  DOSHI, Kshitij Arun ,  FILIPPOU, Miltiadis ,  GANESH, Brinda ,  HERDRICH, Andrew J. ,  IYER, Ravishankar R. ,  JAIN, Nilesh ,  KUMAR, Karthik ,  KUTCH, Patrick G. ,  MACIOCCO, Christian ,  PARKER, Valerie J. ,  PASTOR BENEYTO, Felipe ,  POORNACHANDRAN, Rajesh ,  POWER, Damien ,  PRABHAKARAN, Suraj ,  SCHOOLER, Eve M. ,  SMITH, Ned M. ,  SOOD, Kapil ,  TAHHAN, Maryam ,  VERRALL, Timothy ,  VISWANATHAN, Tarun ,  VON BOKERN, Vincent ,  WALSH, Eoin ,  WILLHALM, Thomas ,  SETHURAMAN, Ramanathan ,  PATEL, Rashmin ,  VERPLANKE, Edwin ,  SHAH, Rahul R.

IPC分类号： H04L29/08

公开(公告)号：EP4134821A1

公开(公告)日：2023-02-15

申请号：EP22181918.8

申请日：2022-06-29

申请人： INTEL Corporation

发明人： NURVITADHI, Eriko ,  DAVARE, Abhijit ,  LACEWELL, Chaunte ,  BHIWANDIWALLA, Anahita ,  JAIN, Nilesh ,  POORNACHANDRAN, Rajesh ,  MUNOZ, Juan Pablo ,  BOUTROS, Andrew ,  AKHAURI, Yash

IPC分类号： G06F9/50 ,  G06N3/04

摘要： Methods, apparatus, systems, and articles of manufacture are disclosed for composable machine learning compute nodes. An example apparatus includes interface circuitry to receive a workload, instructions in the apparatus, and processor circuitry to at least one of execute or instantiate the instructions to generate a first configuration of one or more machine-learning models based on a workload, generate a second configuration of hardware, determine an evaluation parameter based on an execution of the workload, the execution of the workload based on the first configuration and the second configuration, and, in response to the evaluation parameter satisfying a threshold, execute the one or more machine-learning models in the first configuration on the hardware in the second configuration, the one or more machine-learning models and the hardware to execute the workload.