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公开(公告)号：EP0524461A3
公开(公告)日：1993-09-01
申请号：EP92111173.8
申请日：1992-07-02
CPC分类号： H04N5/272 , G09G5/14 , G09G5/395 , G09G2340/125
摘要： Method and apparatus for implementing a raster graphic display video data path that provides arbitrary mixing of a plurality of images. The video data path is highly parallelized, and employs parallel devices operating under the control of a set of look-up tables (15). The look-up tables are loadable from a controller, such as a host workstation (14). The raster graphic display video data path functions with unlimited screen resolutions, and also enables a variety of different pixel data formats (15) from a potentially large number of different sources. Outputs from several image sources are mixed under the control of the host workstation, with a resultant pixel value being based on (a) a combined translucency coefficient (alpha) of the images, for each image source, and (b) a window identification number assigned by the host workstation. Pixel value conversion to a common predetermined format provides coherency between pixel values generated by a number of different image sources, such as HDTV and graphics servers. A separate frame buffer (FB-1 to FB-N) is allocated for each of the sources.
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2.发明公开Look-up table based gamma and inverse gamma correction for high-resolution frame buffers 失效Gammakorrektur und invertierte Gammakorrektur mit NachschlagtabellenfürhochauflösendeRasterpuffer。
公开(公告)号：EP0525527A2
公开(公告)日：1993-02-03
申请号：EP92112142.2
申请日：1992-07-16
发明人： Choi, Sung Min , Lumelsky, Leon , Peevers, Alan Wesley , Pittas, John Louis , Swart, Calvin Bruce
IPC分类号： G09G1/28
CPC分类号： G09G5/04 , G09G1/285 , G09G5/39 , G09G2320/0276
摘要： 5 n7 An image display system includes an input to a source (10, 12, 14) of image pixel data wherein each pixel is expressed as an M-bit value within a non-linear range of values. A first LUT (16) is coupled to an output of the source for converting each M-bit pixel value to an N-bit value within a linear range of values. An image memory, or frame buffer (18), has an input coupled to an output of the first LUT for storing the N-bit pixel values. The system further includes a second LUT (20) coupled to an output of the frame buffer for converting N-bit pixel values output by the frame buffer to P-bit pixel values within a non-linear range of values. The converted values are subsequently applied to a display (24). In an exemplary embodiment, the first LUT stores gamma corrected pixel values and the second LUT stores inverse gamma corrected pixel values. Preferably the second LUT stores a plurality of sets of inverse gamma corrected pixel values. Also, the frame buffer stores, for each of the N-bit pixel values, a value that specifies a particular one of the plurality of sets of inverse gamma corrected pixel values for use in converting an associated one of the N-bit pixel values.
摘要翻译： 图像显示系统包括对图像像素数据的源（10,12,14）的输入，其中每个像素被表示为非线性值范围内的M位值。 第一LUT（16）耦合到源的输出端，用于将每个M位像素值转换成线性范围内的N位值。 图像存储器或帧缓冲器（18）具有耦合到第一LUT的输出的输入，用于存储N位像素值。 该系统还包括耦合到帧缓冲器的输出的第二LUT（20），用于将由帧缓冲器输出的N位像素值转换成非线性范围内的P位像素值。 随后将转换的值应用于显示器（24）。 在示例性实施例中，第一LUT存储伽马校正像素值，第二LUT存储反伽马校正像素值。 优选地，第二LUT存储多组反伽马校正像素值。 此外，帧缓冲器对于每个N位像素值存储指定用于转换N位像素值中相关联的一个的多个伽马校正像素值的多个组中的特定一个的值。
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公开(公告)号：EP0419814A3
公开(公告)日：1992-09-30
申请号：EP90114943.5
申请日：1990-08-03
发明人： Lumelsky, Leon , Peevers, Alan W. , Choi, Sung Min
CPC分类号： G09G5/36 , G09G5/14 , G09G5/395 , G09G2340/125
摘要： A locking mechanism is incorporated in a high-resolution video display system including a high-resolution monitor, a computer for providing controls signals to said display system and two high-resolution frame buffers, one for storing computer generated graphics images and one for storing video data both of said buffers being operable under control of said computer for reading out data to the monitor. The locking mechanism includes an output lock functionally located between the output of both of the frame buffers and the high-resolution monitor for preventing video data from overwriting graphics data on said monitor screen. An input lock is also provided for preventing static video data stored in predetermined regions of the video frame buffer from being continually overwritten by motion video data being continually supplied to the video frame buffer. The output lock utilizes an extra bit-plane in the video buffer which stores a predetermined lock pattern and utilizes the normal monitor output port of the buffer operating under control of standard frame buffer addressing circuitry in combination with straight-forward combinational logic to achieve the locking function. The input lock utilizes a small DRAM which stores the input lock pattern data and utilizes this data in conjunction with normal write operations in the video buffer to control circuitry to disable the write function in predetermined regions of the video buffer.
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公开(公告)号：EP0525425A2
公开(公告)日：1993-02-03
申请号：EP92111171.2
申请日：1992-07-02
发明人： Choi, Sung Min , Lumelsky, Leon
CPC分类号： H04N1/64 , G09G5/02 , G09G5/393 , G09G5/395 , G09G2360/123 , H04N19/13 , H04N19/60 , H04N19/91
摘要： An image buffer semiconductor chip is described that includes circuitry for decompressing, compressed pixel image data such data comprising at least a pair of color codes and a bit mask including bit positions with values that define which pixels in a pixel subset of the pixel image receive the encoded color code data. The chip comprises a matrix of memory modules with the pixels in a pixel subset stored in an interleaved fashion, one pixel per module. A data bus communicates with all of the memory modules and broadcasts the color codes. A mask register stores the bit mask when it appears on the data bus. Circuitry selectively writes a first color code in the modules in accordance with bit values of a first kind in the MASK and writes the second color code into the modules in accordance with bit values of a second kind in the MASK.
摘要翻译： 描述了一种图像缓冲半导体芯片，其包括用于解压缩的电路，压缩的像素图像数据（例如包括至少一对颜色代码的数据）和位掩码，所述位掩码包括具有定义像素图像的像素子集中的哪些像素接收 编码的颜色代码数据。 该芯片包括存储器模块矩阵，其中像素子集中的像素以交错方式存储，每个模块一个像素。 数据总线与所有内存模块通信并广播颜色代码。 掩码寄存器在数据总线上出现时存储位掩码。 电路有选择地根据MASK中第一种类的比特值将第一彩色码写入模块中，并根据MASK中第二种比特值将第二彩色码写入模块中。
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公开(公告)号：EP0524468A2
公开(公告)日：1993-01-27
申请号：EP92111313.0
申请日：1992-07-03
IPC分类号： G09G5/14
CPC分类号： G09G5/14 , G09G5/026 , G09G5/36 , G09G5/39 , G09G2340/125
摘要： An image display system (10) includes an image buffer (20,22) having a plurality of addressable locations for storing image pixel data. The system further includes circuitry (24,34,36) coupled to an output of the image buffer for converting image pixel data read therefrom to electrical signals for driving an image display (18). The circuitry is responsive to signals generated by an image display controller (16) for generating one of a plurality of different timing formats for the electrical signals for driving an image display having a specified display resolution. The apparatus further includes circuitry (40,42) for configuring the image buffer in accordance with the specified display resolution. The image buffer is configurable, by example, as two, 2048 location by 1024 location by 24-bit buffers and one 2048 location by 1024 location by 16-bit buffer; or as two, 2048 location by 2048 location by 24-bit buffers and one 2048 location by 2048 location by 16-bit buffer. Each of the 24-bit buffers store R,G,B pixel data and the 16-bit buffers each store a color index (CI) value and an associated window identifier (WID) value. Circuitry at the output of the image buffer decodes CI and WID values into R,G,B pixel data and a Key value specifying pixel mixing.
摘要翻译： 图像显示系统（10）包括具有用于存储图像像素数据的多个可寻址位置的图像缓冲器（20,22）。 该系统还包括耦合到图像缓冲器的输出的电路（24,34,36），用于将从其读取的图像像素数据转换为用于驱动图像显示器（18）的电信号。 电路响应于由图像显示控制器（16）产生的信号，用于产生用于驱动具有指定显示分辨率的图像显示器的电信号的多种不同定时格式之一。 该装置还包括用于根据指定的显示分辨率配置图像缓冲器的电路（40,42）。 图像缓冲器可以通过示例被配置为由24位缓冲器组成的两个2048位置，1024位置，由16位缓冲器组成的一个2048位置由1024位置组成; 或由2048位置由2048位置由24位缓冲区和一个2048位置到2048位置由16位缓冲区。 每个24位缓冲器存储R，G，B像素数据，并且16位缓冲器每个存储颜色索引（CI）值和相关联的窗口标识符（WID）值。 图像缓冲器输出端的电路将CI和WID值解码为R，G，B像素数据以及指定像素混合的Key值。
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6.发明公开
公开(公告)号：EP0419814A2
公开(公告)日：1991-04-03
申请号：EP90114943.5
申请日：1990-08-03
发明人： Lumelsky, Leon , Peevers, Alan W. , Choi, Sung Min
CPC分类号： G09G5/36 , G09G5/14 , G09G5/395 , G09G2340/125
摘要： A locking mechanism is incorporated in a high-resolution video display system including a high-resolution monitor, a computer for providing controls signals to said display system and two high-resolution frame buffers, one for storing computer generated graphics images and one for storing video data both of said buffers being operable under control of said computer for reading out data to the monitor. The locking mechanism includes an output lock functionally located between the output of both of the frame buffers and the high-resolution monitor for preventing video data from overwriting graphics data on said monitor screen. An input lock is also provided for preventing static video data stored in predetermined regions of the video frame buffer from being continually overwritten by motion video data being continually supplied to the video frame buffer.
The output lock utilizes an extra bit-plane in the video buffer which stores a predetermined lock pattern and utilizes the normal monitor output port of the buffer operating under control of standard frame buffer addressing circuitry in combination with straight-forward combinational logic to achieve the locking function.
The input lock utilizes a small DRAM which stores the input lock pattern data and utilizes this data in conjunction with normal write operations in the video buffer to control circuitry to disable the write function in predetermined regions of the video buffer.摘要翻译： 锁定机构是在高分辨率视频显示系统，包括一个高分辨率显示器，用于提供控制信号给所述显示系统和两个高分辨率帧缓冲器，一个用于存储计算机生成的图形图像和一个用于存储视频的计算机并入 说缓冲器的两个数据进行数据读出到监视器是下所述计算机的控制操作。 所述锁定机构包括在输出锁定功能上位于的两个帧缓冲器和用于从上图形覆盖数据防止视频数据的高分辨率显示器的输出端之间在所述监视器屏幕上。 因此，一个输入的锁定提供了一种用于防止存储在视频帧缓冲器的预定区域从通过连续运动的视频数据被连续供应到所述视频帧缓冲区被覆盖的静态视频数据。 输出锁定利用额外位平面在其中存储预定的锁定模式，并利用在标准帧缓冲器的控制下操作的寻址电路结合直截了当组合逻辑来实现锁定缓冲器的正常监控输出端口视频缓冲器 功能。 输入的锁定利用小DRAM存储所述输入的锁定图案数据，并利用与在视频缓冲器正常写操作一起这个数据到控制电路禁用在视频缓冲器的预定区域的写入功能。
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8.发明授权Look-up table based gamma and inverse gamma correction for high-resolution frame buffers 失效Gamma校正和高分辨率光栅缓冲反伽马校正查找表
公开(公告)号：EP0525527B1
公开(公告)日：1997-09-17
申请号：EP92112142.2
申请日：1992-07-16
发明人： Choi, Sung Min , Lumelsky, Leon , Peevers, Alan Wesley , Pittas, John Louis , Swart, Calvin Bruce
IPC分类号： G09G1/28
CPC分类号： G09G5/04 , G09G1/285 , G09G5/39 , G09G2320/0276
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9.发明授权
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10.发明公开Look-up table based gamma and inverse gamma correction for high-resolution frame buffers 失效用于高分辨率帧缓冲器的基于查询表的游戏和反向伽马校正
公开(公告)号：EP0525527A3
公开(公告)日：1994-09-28
申请号：EP92112142.2
申请日：1992-07-16
发明人： Choi, Sung Min , Lumelsky, Leon , Peevers, Alan Wesley , Pittas, John Louis , Swart, Calvin Bruce
IPC分类号： G09G1/28
CPC分类号： G09G5/04 , G09G1/285 , G09G5/39 , G09G2320/0276
摘要： 5 n7 An image display system includes an input to a source (10, 12, 14) of image pixel data wherein each pixel is expressed as an M-bit value within a non-linear range of values. A first LUT (16) is coupled to an output of the source for converting each M-bit pixel value to an N-bit value within a linear range of values. An image memory, or frame buffer (18), has an input coupled to an output of the first LUT for storing the N-bit pixel values. The system further includes a second LUT (20) coupled to an output of the frame buffer for converting N-bit pixel values output by the frame buffer to P-bit pixel values within a non-linear range of values. The converted values are subsequently applied to a display (24). In an exemplary embodiment, the first LUT stores gamma corrected pixel values and the second LUT stores inverse gamma corrected pixel values. Preferably the second LUT stores a plurality of sets of inverse gamma corrected pixel values. Also, the frame buffer stores, for each of the N-bit pixel values, a value that specifies a particular one of the plurality of sets of inverse gamma corrected pixel values for use in converting an associated one of the N-bit pixel values.
摘要翻译： 图像显示系统包括对图像像素数据的源（10,12,14）的输入，其中每个像素被表示为非线性值范围内的M位值。 第一LUT（16）耦合到源的输出端，用于将每个M位像素值转换成线性范围内的N位值。 图像存储器或帧缓冲器（18）具有耦合到第一LUT的输出的输入，用于存储N位像素值。 该系统还包括耦合到帧缓冲器的输出的第二LUT（20），用于将由帧缓冲器输出的N位像素值转换成非线性范围内的P位像素值。 随后将转换的值应用于显示器（24）。 在示例性实施例中，第一LUT存储伽马校正像素值，第二LUT存储反伽马校正像素值。 优选地，第二LUT存储多组反伽马校正像素值。 此外，帧缓冲器对于每个N位像素值存储指定用于转换N位像素值中相关联的一个的多个伽马校正像素值的多个组中的特定一个的值。
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