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1.发明授权
公开(公告)号：EP0319787B1
公开(公告)日：1996-06-19
申请号：EP88119573.9
申请日：1988-11-24
IPC分类号： G06T15/40
CPC分类号： G06T15/503
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公开(公告)号：EP0525425A2
公开(公告)日：1993-02-03
申请号：EP92111171.2
申请日：1992-07-02
发明人： Choi, Sung Min , Lumelsky, Leon
CPC分类号： H04N1/64 , G09G5/02 , G09G5/393 , G09G5/395 , G09G2360/123 , H04N19/13 , H04N19/60 , H04N19/91
摘要： An image buffer semiconductor chip is described that includes circuitry for decompressing, compressed pixel image data such data comprising at least a pair of color codes and a bit mask including bit positions with values that define which pixels in a pixel subset of the pixel image receive the encoded color code data. The chip comprises a matrix of memory modules with the pixels in a pixel subset stored in an interleaved fashion, one pixel per module. A data bus communicates with all of the memory modules and broadcasts the color codes. A mask register stores the bit mask when it appears on the data bus. Circuitry selectively writes a first color code in the modules in accordance with bit values of a first kind in the MASK and writes the second color code into the modules in accordance with bit values of a second kind in the MASK.
摘要翻译： 描述了一种图像缓冲半导体芯片，其包括用于解压缩的电路，压缩的像素图像数据（例如包括至少一对颜色代码的数据）和位掩码，所述位掩码包括具有定义像素图像的像素子集中的哪些像素接收 编码的颜色代码数据。 该芯片包括存储器模块矩阵，其中像素子集中的像素以交错方式存储，每个模块一个像素。 数据总线与所有内存模块通信并广播颜色代码。 掩码寄存器在数据总线上出现时存储位掩码。 电路有选择地根据MASK中第一种类的比特值将第一彩色码写入模块中，并根据MASK中第二种比特值将第二彩色码写入模块中。
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公开(公告)号：EP0524468A2
公开(公告)日：1993-01-27
申请号：EP92111313.0
申请日：1992-07-03
IPC分类号： G09G5/14
CPC分类号： G09G5/14 , G09G5/026 , G09G5/36 , G09G5/39 , G09G2340/125
摘要： An image display system (10) includes an image buffer (20,22) having a plurality of addressable locations for storing image pixel data. The system further includes circuitry (24,34,36) coupled to an output of the image buffer for converting image pixel data read therefrom to electrical signals for driving an image display (18). The circuitry is responsive to signals generated by an image display controller (16) for generating one of a plurality of different timing formats for the electrical signals for driving an image display having a specified display resolution. The apparatus further includes circuitry (40,42) for configuring the image buffer in accordance with the specified display resolution. The image buffer is configurable, by example, as two, 2048 location by 1024 location by 24-bit buffers and one 2048 location by 1024 location by 16-bit buffer; or as two, 2048 location by 2048 location by 24-bit buffers and one 2048 location by 2048 location by 16-bit buffer. Each of the 24-bit buffers store R,G,B pixel data and the 16-bit buffers each store a color index (CI) value and an associated window identifier (WID) value. Circuitry at the output of the image buffer decodes CI and WID values into R,G,B pixel data and a Key value specifying pixel mixing.
摘要翻译： 图像显示系统（10）包括具有用于存储图像像素数据的多个可寻址位置的图像缓冲器（20,22）。 该系统还包括耦合到图像缓冲器的输出的电路（24,34,36），用于将从其读取的图像像素数据转换为用于驱动图像显示器（18）的电信号。 电路响应于由图像显示控制器（16）产生的信号，用于产生用于驱动具有指定显示分辨率的图像显示器的电信号的多种不同定时格式之一。 该装置还包括用于根据指定的显示分辨率配置图像缓冲器的电路（40,42）。 图像缓冲器可以通过示例被配置为由24位缓冲器组成的两个2048位置，1024位置，由16位缓冲器组成的一个2048位置由1024位置组成; 或由2048位置由2048位置由24位缓冲区和一个2048位置到2048位置由16位缓冲区。 每个24位缓冲器存储R，G，B像素数据，并且16位缓冲器每个存储颜色索引（CI）值和相关联的窗口标识符（WID）值。 图像缓冲器输出端的电路将CI和WID值解码为R，G，B像素数据以及指定像素混合的Key值。
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4.发明公开
公开(公告)号：EP0419814A2
公开(公告)日：1991-04-03
申请号：EP90114943.5
申请日：1990-08-03
发明人： Lumelsky, Leon , Peevers, Alan W. , Choi, Sung Min
CPC分类号： G09G5/36 , G09G5/14 , G09G5/395 , G09G2340/125
摘要： A locking mechanism is incorporated in a high-resolution video display system including a high-resolution monitor, a computer for providing controls signals to said display system and two high-resolution frame buffers, one for storing computer generated graphics images and one for storing video data both of said buffers being operable under control of said computer for reading out data to the monitor. The locking mechanism includes an output lock functionally located between the output of both of the frame buffers and the high-resolution monitor for preventing video data from overwriting graphics data on said monitor screen. An input lock is also provided for preventing static video data stored in predetermined regions of the video frame buffer from being continually overwritten by motion video data being continually supplied to the video frame buffer.
The output lock utilizes an extra bit-plane in the video buffer which stores a predetermined lock pattern and utilizes the normal monitor output port of the buffer operating under control of standard frame buffer addressing circuitry in combination with straight-forward combinational logic to achieve the locking function.
The input lock utilizes a small DRAM which stores the input lock pattern data and utilizes this data in conjunction with normal write operations in the video buffer to control circuitry to disable the write function in predetermined regions of the video buffer.摘要翻译： 锁定机构是在高分辨率视频显示系统，包括一个高分辨率显示器，用于提供控制信号给所述显示系统和两个高分辨率帧缓冲器，一个用于存储计算机生成的图形图像和一个用于存储视频的计算机并入 说缓冲器的两个数据进行数据读出到监视器是下所述计算机的控制操作。 所述锁定机构包括在输出锁定功能上位于的两个帧缓冲器和用于从上图形覆盖数据防止视频数据的高分辨率显示器的输出端之间在所述监视器屏幕上。 因此，一个输入的锁定提供了一种用于防止存储在视频帧缓冲器的预定区域从通过连续运动的视频数据被连续供应到所述视频帧缓冲区被覆盖的静态视频数据。 输出锁定利用额外位平面在其中存储预定的锁定模式，并利用在标准帧缓冲器的控制下操作的寻址电路结合直截了当组合逻辑来实现锁定缓冲器的正常监控输出端口视频缓冲器 功能。 输入的锁定利用小DRAM存储所述输入的锁定图案数据，并利用与在视频缓冲器正常写操作一起这个数据到控制电路禁用在视频缓冲器的预定区域的写入功能。
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5.发明公开
公开(公告)号：EP0384419A2
公开(公告)日：1990-08-29
申请号：EP90103282.1
申请日：1990-02-21
CPC分类号： H04N9/641 , G09G5/14 , G09G5/391 , G09G2340/125
摘要： A method for mapping television images onto a graphics screen which can employ a standard digital-television technique to process the television signal is provided. The present invention is concerned with the sampling and storing of a color-television signal in accordance with both the requirements of digital television and the requirements of graphics displays - including windowing requirements - such as used with computers and computer workstations. The invention provides a method of contracting or expanding live color television images, which preferably had been sampled in accordance with a standard digital-television technique, while providing an output of graphics image of a reasonable visual quality for the graphics display.
摘要翻译： 提供了一种用于将电视图像映射到可以采用标准数字电视技术来处理电视信号的图形屏幕上的方法。 本发明涉及根据数字电视的要求和图形显示器的要求（包括窗口化要求）（例如与计算机和计算机工作站一起使用）对彩色电视信号的采样和存储。 本发明提供了一种收缩或扩大直播彩色电视图像的方法，其优选地已经根据标准数字电视技术被采样，同时为图形显示提供合理的视觉质量的图形图像的输出。
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6.发明公开
公开(公告)号：EP0319787A2
公开(公告)日：1989-06-14
申请号：EP88119573.9
申请日：1988-11-24
IPC分类号： G06T15/40
CPC分类号： G06T15/503
摘要： The present invention comprises a method for utilizing an socalled SIMD computer architecture in conjunction with a host processor and coordinate processor to render quality, three-dimensional, anti-aliased shaded color images into the frame buffer of a video display system. The method includes a parallel algorithm for rendering an important graphic primitive for accomplishing the production of a smoothly shaded color three-dimensional triangle with anti-aliased edges. By taking advantage of the SIMD architecture and said parallel algorithm, the very time consuming pixel by pixel computations are broken down for parallel execution. A single coordinate processor computes and transmits an overall triangle record which is essentially the same for all blocks of pixels within a given bounding box which box in turn surrounds each triangle. The individual pixel data is produced by a group of M x N pixel processors and stored in the frame buffer in a series of repetitive steps wherein each step corresponds to the processing of an M x N block of pixels within the bounding box of the triangle. Thus, each pixel processor performs the same operation, modifying its computations in accordance with triangle data received from the coordinate processor and positional data unique to its own sequential connectivity to the frame buffer, thus allowing parallel access to the frame buffer.
摘要翻译： 本发明包括一种用于与主机处理器结合所谓的SIMD计算机体系结构的利用和坐标处理器渲染质量，三维，抗混叠阴影彩色图像转换成的视频显示系统的帧缓冲器中，该方法包括一 并行算法用于实现生产平滑着色的彩色的三维三角形的具有抗混叠边缘的重要图元渲染。 通过取SIMD架构和算法所述平行的优点，由像素计算的非常费时的像素被分解为并行执行。 单个处理器计算坐标和整体上三角形记录传输所有这实质上是对于给定的边界框内反过来哪个框围绕每个三角形像素的所有块是相同的。 各个像素数据是由一组M×N个像素处理器的产生并存储在帧缓冲器中的一系列重复的步骤worin每个步骤对应于三角形的边界框内的像素的M×N个块的处理。 因此，每个像素处理器执行相同的手术，与从处理器接收和坐标位置数据独特到它自己的顺序连接到帧缓冲器三角形数据，从而允许以该帧缓冲器的并行访问修改其计算在雅舞蹈。
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8.发明授权Look-up table based gamma and inverse gamma correction for high-resolution frame buffers 失效Gamma校正和高分辨率光栅缓冲反伽马校正查找表
公开(公告)号：EP0525527B1
公开(公告)日：1997-09-17
申请号：EP92112142.2
申请日：1992-07-16
发明人： Choi, Sung Min , Lumelsky, Leon , Peevers, Alan Wesley , Pittas, John Louis , Swart, Calvin Bruce
IPC分类号： G09G1/28
CPC分类号： G09G5/04 , G09G1/285 , G09G5/39 , G09G2320/0276
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9.发明授权Triple field buffer for television image storage and visualization on raster graphics display 失效用于电视图像的存储和显示图形光栅显示装置上三重帧缓冲器
公开(公告)号：EP0462396B1
公开(公告)日：1997-01-02
申请号：EP91107863.2
申请日：1991-05-15
发明人： Lumelsky, Leon
IPC分类号： H04N5/44
CPC分类号： H04N7/012 , G09G5/39 , G09G5/397 , G09G2310/0229
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