利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

6 条记录 (耗时 0.011 秒)

    Oscillator circuit incorporated in a semiconductor circuit
    2.
    发明公开
    Oscillator circuit incorporated in a semiconductor circuit 失效
    在半导体电路中并入的振荡器电路

    公开(公告)号：EP0398331A3

    公开(公告)日：1993-05-26

    申请号：EP90109342.7

    申请日：1990-05-17

    申请人： KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA MICRO-ELECTRONICS CORPORATION

    发明人： Kondo, Hitoshi, c/o Intellectual Property Div. ,  Suwabe, Hiroyuki, c/o Intellectual Property Div. ,  Kojima, Aiki, c/o Intellectual Property Div.

    IPC分类号： H03B5/32 ,  H01L27/06

    CPC分类号： H03K3/0307 ,  H01L27/092

    摘要： An oscillator circuit (OSC) incorporated in a semi­conductor integrated circuit and comprising an oscilla­tion input terminal (Xin), an oscillator output terminal (Xout), an inverting logic circuit (IV1), and a trans­mission gate (TR˝). The terminals (Zin) and (Zout) are connected to an external oscillator (X'tal). The inverting logic circuit (IV1) comprises an N-type MOS transistor (N2) and a P-type MOS transistor (P2). The input and output terminals of the logic circuit (IV1) are connected to the oscillation input and output termi­nals (Xin, Xout), respectively. The transmission gate comprises an N-type MOS transistor (N1˝) and a P-type MOS transistor (P1˝). Either MOS transistor has a source electrode and a drain electrode, one of which is connected to said oscillation input terminal (Xin), and the other of which is said oscillation output terminal (Xout). The gate-insulating film at least one of said MOS transistors incorporated in the transmission gate is thicker than those of other MOS transistors formed on the semiconductor substrate.

    Oscillator circuit incorporated in a semiconductor circuit
    3.
    发明公开
    Oscillator circuit incorporated in a semiconductor circuit 失效
    Oszillatorschaltkreis innerhalb eines Halbleiterschaltkreises。

    公开(公告)号：EP0398331A2

    公开(公告)日：1990-11-22

    申请号：EP90109342.7

    申请日：1990-05-17

    申请人： KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA MICRO-ELECTRONICS CORPORATION

    发明人： Kondo, Hitoshi, c/o Intellectual Property Div. ,  Suwabe, Hiroyuki, c/o Intellectual Property Div. ,  Kojima, Aiki, c/o Intellectual Property Div.

    IPC分类号： H03B5/32 ,  H01L27/06

    CPC分类号： H03K3/0307 ,  H01L27/092

    摘要： An oscillator circuit (OSC) incorporated in a semi­conductor integrated circuit and comprising an oscilla­tion input terminal (Xin), an oscillator output terminal (Xout), an inverting logic circuit (IV1), and a trans­mission gate (TR˝). The terminals (Zin) and (Zout) are connected to an external oscillator (X'tal). The inverting logic circuit (IV1) comprises an N-type MOS transistor (N2) and a P-type MOS transistor (P2). The input and output terminals of the logic circuit (IV1) are connected to the oscillation input and output termi­nals (Xin, Xout), respectively. The transmission gate comprises an N-type MOS transistor (N1˝) and a P-type MOS transistor (P1˝). Either MOS transistor has a source electrode and a drain electrode, one of which is connected to said oscillation input terminal (Xin), and the other of which is said oscillation output terminal (Xout). The gate-insulating film at least one of said MOS transistors incorporated in the transmission gate is thicker than those of other MOS transistors formed on the semiconductor substrate.

    摘要翻译： 包括在半导体集成电路中并包括振荡输入端（昕），振荡器输出端（Xout），反相逻辑电路（IV1）和传输门（TRsec）的振荡电路（OSC）。 端子（Zin）和（Zout）连接到外部振荡器（X'tal）。 反相逻辑电路（IV1）包括N型MOS晶体管（N2）和P型MOS晶体管（P2）。 逻辑电路（IV1）的输入和输出端分别连接到振荡输入和输出端子（Xin，Xout）。 传输门包括N型MOS晶体管（N1sec）和P型MOS晶体管（P1sec）。 MOS晶体管具有源电极和漏极，其中一个连接到所述振荡输入端（鑫），另一个是所述振荡输出端（Xout）。 结合在传输门中的至少一个所述MOS晶体管的栅极绝缘膜比形成在半导体衬底上的其它MOS晶体管的栅极绝缘膜厚。

    Nonvolatile semiconductor memory system
    6.
    发明公开
    Nonvolatile semiconductor memory system 失效
    NichtflüchtigesHalbleiterspeichersystem。

    公开(公告)号：EP0438050A2

    公开(公告)日：1991-07-24

    申请号：EP91100033.9

    申请日：1991-01-02

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Kondo, Hitoshi, c/o Intellectual Property Div. ,  Yamamoto, Tetsuya, c/o Intellectual Property Div. ,  Saeki, Yukihiro, c/o Intellectual Property Div.

    IPC分类号： G11C16/06

    CPC分类号： G11C16/105 ,  G11C16/102 ,  G11C16/34

    摘要： An EPROM integrated circuit (20) includes a plurality of banks. When a data write operation is to be performed for this EEPROM integrated circuit (20), a bank which is used once is not used again, but the operation is constantly performed for new banks. In order to select a bank, a write number storage area (21) is provided in the EPROM integrated circuit (20), and the contents of the write number storage area (21) are updated by a write number updating circuit (29) each time the write operation is performed for a new bank.

    摘要翻译： EPROM集成电路（20）包括多个存储体。 当对该EEPROM集成电路（20）执行数据写入操作时，一次使用的存储体不再被使用，但是对于新的存储体不断地执行操作。 为了选择存储体，在EPROM集成电路（20）中设置写入存储区域（21），写入数量存储区域（21）的内容由写入数量更新电路（29）进行更新 对新银行执行写入操作的时间。